254 lines
6.2 KiB
C
254 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
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*
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* Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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*
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* This driver has been based on the spi-gpio.c:
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* Copyright (C) 2006,2008 David Brownell
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_data/spi-ath79.h>
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#define DRV_NAME "ath79-spi"
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#define ATH79_SPI_RRW_DELAY_FACTOR 12000
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#define MHZ (1000 * 1000)
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#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
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#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
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#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
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#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
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#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
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#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
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#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
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#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
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struct ath79_spi {
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struct spi_bitbang bitbang;
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u32 ioc_base;
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u32 reg_ctrl;
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void __iomem *base;
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struct clk *clk;
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unsigned int rrw_delay;
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};
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static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
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{
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return ioread32(sp->base + reg);
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}
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static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
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{
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iowrite32(val, sp->base + reg);
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}
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static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
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{
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return spi_master_get_devdata(spi->master);
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}
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static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
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{
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if (nsecs > sp->rrw_delay)
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ndelay(nsecs - sp->rrw_delay);
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}
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static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
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u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
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if (cs_high)
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sp->ioc_base |= cs_bit;
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else
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sp->ioc_base &= ~cs_bit;
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
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}
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static void ath79_spi_enable(struct ath79_spi *sp)
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{
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/* enable GPIO mode */
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ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
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/* save CTRL register */
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sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
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sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
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/* clear clk and mosi in the base state */
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sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
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/* TODO: setup speed? */
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ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
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}
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static void ath79_spi_disable(struct ath79_spi *sp)
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{
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/* restore CTRL register */
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ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
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/* disable GPIO mode */
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ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
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}
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static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
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u32 word, u8 bits, unsigned flags)
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{
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struct ath79_spi *sp = ath79_spidev_to_sp(spi);
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u32 ioc = sp->ioc_base;
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/* clock starts at inactive polarity */
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for (word <<= (32 - bits); likely(bits); bits--) {
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u32 out;
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if (word & (1 << 31))
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out = ioc | AR71XX_SPI_IOC_DO;
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else
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out = ioc & ~AR71XX_SPI_IOC_DO;
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/* setup MSB (to slave) on trailing edge */
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
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ath79_spi_delay(sp, nsecs);
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
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ath79_spi_delay(sp, nsecs);
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if (bits == 1)
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ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
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word <<= 1;
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}
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return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
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}
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static int ath79_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct ath79_spi *sp;
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struct ath79_spi_platform_data *pdata;
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struct resource *r;
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unsigned long rate;
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int ret;
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master = spi_alloc_master(&pdev->dev, sizeof(*sp));
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if (master == NULL) {
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dev_err(&pdev->dev, "failed to allocate spi master\n");
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return -ENOMEM;
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}
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sp = spi_master_get_devdata(master);
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master->dev.of_node = pdev->dev.of_node;
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platform_set_drvdata(pdev, sp);
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pdata = dev_get_platdata(&pdev->dev);
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master->use_gpio_descriptors = true;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
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master->setup = spi_bitbang_setup;
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master->cleanup = spi_bitbang_cleanup;
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if (pdata) {
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master->bus_num = pdata->bus_num;
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master->num_chipselect = pdata->num_chipselect;
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}
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sp->bitbang.master = master;
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sp->bitbang.chipselect = ath79_spi_chipselect;
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sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
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sp->bitbang.flags = SPI_CS_HIGH;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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sp->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(sp->base)) {
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ret = PTR_ERR(sp->base);
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goto err_put_master;
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}
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sp->clk = devm_clk_get(&pdev->dev, "ahb");
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if (IS_ERR(sp->clk)) {
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ret = PTR_ERR(sp->clk);
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goto err_put_master;
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}
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ret = clk_prepare_enable(sp->clk);
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if (ret)
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goto err_put_master;
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rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
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if (!rate) {
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ret = -EINVAL;
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goto err_clk_disable;
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}
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sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
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dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
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sp->rrw_delay);
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ath79_spi_enable(sp);
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ret = spi_bitbang_start(&sp->bitbang);
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if (ret)
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goto err_disable;
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return 0;
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err_disable:
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ath79_spi_disable(sp);
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err_clk_disable:
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clk_disable_unprepare(sp->clk);
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err_put_master:
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spi_master_put(sp->bitbang.master);
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return ret;
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}
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static int ath79_spi_remove(struct platform_device *pdev)
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{
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struct ath79_spi *sp = platform_get_drvdata(pdev);
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spi_bitbang_stop(&sp->bitbang);
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ath79_spi_disable(sp);
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clk_disable_unprepare(sp->clk);
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spi_master_put(sp->bitbang.master);
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return 0;
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}
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static void ath79_spi_shutdown(struct platform_device *pdev)
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{
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ath79_spi_remove(pdev);
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}
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static const struct of_device_id ath79_spi_of_match[] = {
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{ .compatible = "qca,ar7100-spi", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
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static struct platform_driver ath79_spi_driver = {
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.probe = ath79_spi_probe,
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.remove = ath79_spi_remove,
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.shutdown = ath79_spi_shutdown,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = ath79_spi_of_match,
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},
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};
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module_platform_driver(ath79_spi_driver);
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MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
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MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" DRV_NAME);
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