543 lines
13 KiB
C
543 lines
13 KiB
C
/*
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* @file op_model_amd.c
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* athlon / K7 / K8 / Family 10h model-specific MSR operations
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*
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* @remark Copyright 2002-2009 OProfile authors
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* @remark Read the file COPYING
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*
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* @author John Levon
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* @author Philippe Elie
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* @author Graydon Hoare
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* @author Robert Richter <robert.richter@amd.com>
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* @author Barry Kasindorf <barry.kasindorf@amd.com>
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* @author Jason Yeh <jason.yeh@amd.com>
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* @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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*/
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#include <linux/oprofile.h>
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#include <linux/device.h>
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#include <linux/pci.h>
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#include <linux/percpu.h>
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#include <asm/ptrace.h>
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#include <asm/msr.h>
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#include <asm/nmi.h>
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#include <asm/apic.h>
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#include <asm/processor.h>
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#include "op_x86_model.h"
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#include "op_counter.h"
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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#define NUM_VIRT_COUNTERS 32
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#else
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#define NUM_VIRT_COUNTERS 0
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#endif
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#define OP_EVENT_MASK 0x0FFF
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#define OP_CTR_OVERFLOW (1ULL<<31)
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#define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
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static int num_counters;
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static unsigned long reset_value[OP_MAX_COUNTER];
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#define IBS_FETCH_SIZE 6
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#define IBS_OP_SIZE 12
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static u32 ibs_caps;
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struct ibs_config {
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unsigned long op_enabled;
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unsigned long fetch_enabled;
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unsigned long max_cnt_fetch;
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unsigned long max_cnt_op;
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unsigned long rand_en;
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unsigned long dispatched_ops;
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unsigned long branch_target;
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};
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struct ibs_state {
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u64 ibs_op_ctl;
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int branch_target;
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unsigned long sample_size;
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};
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static struct ibs_config ibs_config;
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static struct ibs_state ibs_state;
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/*
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* IBS randomization macros
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*/
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#define IBS_RANDOM_BITS 12
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#define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1)
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#define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5))
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/*
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* 16-bit Linear Feedback Shift Register (LFSR)
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*
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* 16 14 13 11
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* Feedback polynomial = X + X + X + X + 1
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*/
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static unsigned int lfsr_random(void)
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{
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static unsigned int lfsr_value = 0xF00D;
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unsigned int bit;
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/* Compute next bit to shift in */
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bit = ((lfsr_value >> 0) ^
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(lfsr_value >> 2) ^
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(lfsr_value >> 3) ^
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(lfsr_value >> 5)) & 0x0001;
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/* Advance to next register value */
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lfsr_value = (lfsr_value >> 1) | (bit << 15);
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return lfsr_value;
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}
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/*
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* IBS software randomization
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*
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* The IBS periodic op counter is randomized in software. The lower 12
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* bits of the 20 bit counter are randomized. IbsOpCurCnt is
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* initialized with a 12 bit random value.
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*/
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static inline u64 op_amd_randomize_ibs_op(u64 val)
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{
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unsigned int random = lfsr_random();
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if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
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/*
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* Work around if the hw can not write to IbsOpCurCnt
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*
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* Randomize the lower 8 bits of the 16 bit
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* IbsOpMaxCnt [15:0] value in the range of -128 to
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* +127 by adding/subtracting an offset to the
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* maximum count (IbsOpMaxCnt).
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*
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* To avoid over or underflows and protect upper bits
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* starting at bit 16, the initial value for
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* IbsOpMaxCnt must fit in the range from 0x0081 to
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* 0xff80.
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*/
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val += (s8)(random >> 4);
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else
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val |= (u64)(random & IBS_RANDOM_MASK) << 32;
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return val;
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}
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static inline void
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op_amd_handle_ibs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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u64 val, ctl;
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struct op_entry entry;
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if (!ibs_caps)
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return;
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if (ibs_config.fetch_enabled) {
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rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
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if (ctl & IBS_FETCH_VAL) {
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rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
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oprofile_write_reserve(&entry, regs, val,
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IBS_FETCH_CODE, IBS_FETCH_SIZE);
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oprofile_add_data64(&entry, val);
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oprofile_add_data64(&entry, ctl);
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rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
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oprofile_add_data64(&entry, val);
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oprofile_write_commit(&entry);
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/* reenable the IRQ */
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ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT);
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ctl |= IBS_FETCH_ENABLE;
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wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
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}
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}
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if (ibs_config.op_enabled) {
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rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
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if (ctl & IBS_OP_VAL) {
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rdmsrl(MSR_AMD64_IBSOPRIP, val);
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oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE,
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ibs_state.sample_size);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSOPDATA, val);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSOPDATA2, val);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSOPDATA3, val);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSDCLINAD, val);
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oprofile_add_data64(&entry, val);
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rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
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oprofile_add_data64(&entry, val);
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if (ibs_state.branch_target) {
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rdmsrl(MSR_AMD64_IBSBRTARGET, val);
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oprofile_add_data(&entry, (unsigned long)val);
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}
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oprofile_write_commit(&entry);
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/* reenable the IRQ */
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ctl = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
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wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
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}
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}
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}
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static inline void op_amd_start_ibs(void)
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{
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u64 val;
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if (!ibs_caps)
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return;
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memset(&ibs_state, 0, sizeof(ibs_state));
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/*
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* Note: Since the max count settings may out of range we
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* write back the actual used values so that userland can read
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* it.
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*/
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if (ibs_config.fetch_enabled) {
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val = ibs_config.max_cnt_fetch >> 4;
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val = min(val, IBS_FETCH_MAX_CNT);
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ibs_config.max_cnt_fetch = val << 4;
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val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
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val |= IBS_FETCH_ENABLE;
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wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
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}
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if (ibs_config.op_enabled) {
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val = ibs_config.max_cnt_op >> 4;
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if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
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/*
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* IbsOpCurCnt not supported. See
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* op_amd_randomize_ibs_op() for details.
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*/
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val = clamp(val, 0x0081ULL, 0xFF80ULL);
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ibs_config.max_cnt_op = val << 4;
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} else {
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/*
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* The start value is randomized with a
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* positive offset, we need to compensate it
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* with the half of the randomized range. Also
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* avoid underflows.
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*/
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val += IBS_RANDOM_MAXCNT_OFFSET;
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if (ibs_caps & IBS_CAPS_OPCNTEXT)
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val = min(val, IBS_OP_MAX_CNT_EXT);
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else
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val = min(val, IBS_OP_MAX_CNT);
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ibs_config.max_cnt_op =
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(val - IBS_RANDOM_MAXCNT_OFFSET) << 4;
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}
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val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT);
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val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
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val |= IBS_OP_ENABLE;
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ibs_state.ibs_op_ctl = val;
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ibs_state.sample_size = IBS_OP_SIZE;
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if (ibs_config.branch_target) {
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ibs_state.branch_target = 1;
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ibs_state.sample_size++;
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}
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val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);
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wrmsrl(MSR_AMD64_IBSOPCTL, val);
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}
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}
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static void op_amd_stop_ibs(void)
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{
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if (!ibs_caps)
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return;
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if (ibs_config.fetch_enabled)
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/* clear max count and enable */
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wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
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if (ibs_config.op_enabled)
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/* clear max count and enable */
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wrmsrl(MSR_AMD64_IBSOPCTL, 0);
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}
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/* enable active counters */
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for (i = 0; i < num_counters; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!reset_value[virt])
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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#endif
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/* functions for op_amd_spec */
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static void op_amd_shutdown(struct op_msrs const * const msrs)
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{
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int i;
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for (i = 0; i < num_counters; ++i) {
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if (!msrs->counters[i].addr)
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continue;
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
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}
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}
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static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
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{
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int i;
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for (i = 0; i < num_counters; i++) {
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if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
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goto fail;
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if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
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release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
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goto fail;
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}
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/* both registers must be reserved */
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if (num_counters == AMD64_NUM_COUNTERS_CORE) {
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msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);
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msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);
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} else {
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msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
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msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
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}
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continue;
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fail:
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if (!counter_config[i].enabled)
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continue;
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op_x86_warn_reserved(i);
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op_amd_shutdown(msrs);
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return -EBUSY;
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}
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return 0;
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}
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static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/* setup reset_value */
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for (i = 0; i < OP_MAX_COUNTER; ++i) {
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if (counter_config[i].enabled
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&& msrs->counters[op_x86_virt_to_phys(i)].addr)
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reset_value[i] = counter_config[i].count;
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else
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reset_value[i] = 0;
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}
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/* clear all counters */
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for (i = 0; i < num_counters; ++i) {
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if (!msrs->controls[i].addr)
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
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op_x86_warn_in_use(i);
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val &= model->reserved;
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wrmsrl(msrs->controls[i].addr, val);
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/*
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* avoid a false detection of ctr overflows in NMI
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* handler
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*/
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wrmsrl(msrs->counters[i].addr, -1LL);
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}
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/* enable active counters */
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for (i = 0; i < num_counters; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!reset_value[virt])
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continue;
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/* setup counter registers */
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
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/* setup control registers */
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rdmsrl(msrs->controls[i].addr, val);
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val &= model->reserved;
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val |= op_x86_get_ctrl(model, &counter_config[virt]);
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wrmsrl(msrs->controls[i].addr, val);
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}
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}
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static int op_amd_check_ctrs(struct pt_regs * const regs,
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struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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for (i = 0; i < num_counters; ++i) {
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int virt = op_x86_phys_to_virt(i);
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if (!reset_value[virt])
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continue;
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rdmsrl(msrs->counters[i].addr, val);
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/* bit is clear if overflowed: */
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if (val & OP_CTR_OVERFLOW)
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continue;
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oprofile_add_sample(regs, virt);
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wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
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}
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op_amd_handle_ibs(regs, msrs);
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/* See op_model_ppro.c */
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return 1;
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}
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static void op_amd_start(struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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for (i = 0; i < num_counters; ++i) {
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if (!reset_value[op_x86_phys_to_virt(i)])
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val |= ARCH_PERFMON_EVENTSEL_ENABLE;
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wrmsrl(msrs->controls[i].addr, val);
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}
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op_amd_start_ibs();
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}
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static void op_amd_stop(struct op_msrs const * const msrs)
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{
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u64 val;
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int i;
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/*
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* Subtle: stop on all counters to avoid race with setting our
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* pm callback
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*/
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for (i = 0; i < num_counters; ++i) {
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if (!reset_value[op_x86_phys_to_virt(i)])
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continue;
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rdmsrl(msrs->controls[i].addr, val);
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val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
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wrmsrl(msrs->controls[i].addr, val);
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}
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op_amd_stop_ibs();
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}
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/*
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* check and reserve APIC extended interrupt LVT offset for IBS if
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* available
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*/
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static void init_ibs(void)
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{
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ibs_caps = get_ibs_caps();
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if (!ibs_caps)
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return;
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printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n", ibs_caps);
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}
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static int (*create_arch_files)(struct dentry *root);
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static int setup_ibs_files(struct dentry *root)
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{
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struct dentry *dir;
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int ret = 0;
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/* architecture specific files */
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if (create_arch_files)
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ret = create_arch_files(root);
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if (ret)
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return ret;
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if (!ibs_caps)
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return ret;
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/* model specific files */
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/* setup some reasonable defaults */
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memset(&ibs_config, 0, sizeof(ibs_config));
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ibs_config.max_cnt_fetch = 250000;
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ibs_config.max_cnt_op = 250000;
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if (ibs_caps & IBS_CAPS_FETCHSAM) {
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dir = oprofilefs_mkdir(root, "ibs_fetch");
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oprofilefs_create_ulong(dir, "enable",
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&ibs_config.fetch_enabled);
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oprofilefs_create_ulong(dir, "max_count",
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&ibs_config.max_cnt_fetch);
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oprofilefs_create_ulong(dir, "rand_enable",
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&ibs_config.rand_en);
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}
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if (ibs_caps & IBS_CAPS_OPSAM) {
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dir = oprofilefs_mkdir(root, "ibs_op");
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oprofilefs_create_ulong(dir, "enable",
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&ibs_config.op_enabled);
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oprofilefs_create_ulong(dir, "max_count",
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&ibs_config.max_cnt_op);
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if (ibs_caps & IBS_CAPS_OPCNT)
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oprofilefs_create_ulong(dir, "dispatched_ops",
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&ibs_config.dispatched_ops);
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if (ibs_caps & IBS_CAPS_BRNTRGT)
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oprofilefs_create_ulong(dir, "branch_target",
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&ibs_config.branch_target);
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}
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return 0;
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}
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struct op_x86_model_spec op_amd_spec;
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static int op_amd_init(struct oprofile_operations *ops)
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{
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init_ibs();
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create_arch_files = ops->create_files;
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ops->create_files = setup_ibs_files;
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if (boot_cpu_data.x86 == 0x15) {
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num_counters = AMD64_NUM_COUNTERS_CORE;
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} else {
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num_counters = AMD64_NUM_COUNTERS;
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}
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op_amd_spec.num_counters = num_counters;
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op_amd_spec.num_controls = num_counters;
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op_amd_spec.num_virt_counters = max(num_counters, NUM_VIRT_COUNTERS);
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|
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return 0;
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}
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|
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struct op_x86_model_spec op_amd_spec = {
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/* num_counters/num_controls filled in at runtime */
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|
.reserved = MSR_AMD_EVENTSEL_RESERVED,
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|
.event_mask = OP_EVENT_MASK,
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.init = op_amd_init,
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.fill_in_addresses = &op_amd_fill_in_addresses,
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.setup_ctrs = &op_amd_setup_ctrs,
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.check_ctrs = &op_amd_check_ctrs,
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.start = &op_amd_start,
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.stop = &op_amd_stop,
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|
.shutdown = &op_amd_shutdown,
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|
#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
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|
.switch_ctrl = &op_mux_switch_ctrl,
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|
#endif
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|
};
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