296 lines
8.2 KiB
C
296 lines
8.2 KiB
C
/*
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* Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2000 Mark Lord <mlord@pobox.com>
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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* Development of this chipset driver was funded
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* by the nice folks at National Semiconductor.
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*
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* Documentation:
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* CS5530 documentation available from National Semiconductor.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#define DRV_NAME "cs5530"
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/*
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* Here are the standard PIO mode 0-4 timings for each "format".
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* Format-0 uses fast data reg timings, with slower command reg timings.
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* Format-1 uses fast timings for all registers, but won't work with all drives.
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*/
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static unsigned int cs5530_pio_timings[2][5] = {
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{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
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{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
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};
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/*
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* After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
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*/
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#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
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#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
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/**
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* cs5530_set_pio_mode - set host controller for PIO mode
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* @drive: drive
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* @pio: PIO mode number
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*
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* Handles setting of PIO mode for the chipset.
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*
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* The init_hwif_cs5530() routine guarantees that all drives
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* will have valid default PIO timings set up before we get here.
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*/
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static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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unsigned long basereg = CS5530_BASEREG(drive->hwif);
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unsigned int format = (inl(basereg + 4) >> 31) & 1;
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outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
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}
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/**
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* cs5530_udma_filter - UDMA filter
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* @drive: drive
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*
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* cs5530_udma_filter() does UDMA mask filtering for the given drive
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* taking into the consideration capabilities of the mate device.
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*
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* The CS5530 specifies that two drives sharing a cable cannot mix
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* UDMA/MDMA. It has to be one or the other, for the pair, though
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* different timings can still be chosen for each drive. We could
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* set the appropriate timing bits on the fly, but that might be
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* a bit confusing. So, for now we statically handle this requirement
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* by looking at our mate drive to see what it is capable of, before
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* choosing a mode for our own drive.
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*
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* Note: This relies on the fact we never fail from UDMA to MWDMA2
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* but instead drop to PIO.
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*/
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static u8 cs5530_udma_filter(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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ide_drive_t *mate = ide_get_pair_dev(drive);
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u16 *mateid;
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u8 mask = hwif->ultra_mask;
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if (mate == NULL)
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goto out;
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mateid = mate->id;
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if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
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if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
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(mateid[ATA_ID_UDMA_MODES] & 7))
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goto out;
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if ((mateid[ATA_ID_FIELD_VALID] & 2) &&
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(mateid[ATA_ID_MWDMA_MODES] & 7))
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mask = 0;
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}
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out:
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return mask;
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}
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static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
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{
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unsigned long basereg;
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unsigned int reg, timings = 0;
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switch (mode) {
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case XFER_UDMA_0: timings = 0x00921250; break;
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case XFER_UDMA_1: timings = 0x00911140; break;
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case XFER_UDMA_2: timings = 0x00911030; break;
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case XFER_MW_DMA_0: timings = 0x00077771; break;
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case XFER_MW_DMA_1: timings = 0x00012121; break;
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case XFER_MW_DMA_2: timings = 0x00002020; break;
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}
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basereg = CS5530_BASEREG(drive->hwif);
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reg = inl(basereg + 4); /* get drive0 config register */
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timings |= reg & 0x80000000; /* preserve PIO format bit */
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if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
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outl(timings, basereg + 4); /* write drive0 config register */
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} else {
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if (timings & 0x00100000)
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reg |= 0x00100000; /* enable UDMA timings for both drives */
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else
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reg &= ~0x00100000; /* disable UDMA timings for both drives */
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outl(reg, basereg + 4); /* write drive0 config register */
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outl(timings, basereg + 12); /* write drive1 config register */
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}
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}
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/**
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* init_chipset_5530 - set up 5530 bridge
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* @dev: PCI device
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*
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* Initialize the cs5530 bridge for reliable IDE DMA operation.
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*/
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static int init_chipset_cs5530(struct pci_dev *dev)
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{
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struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
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if (pci_resource_start(dev, 4) == 0)
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return -EFAULT;
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dev = NULL;
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while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
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switch (dev->device) {
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case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
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master_0 = pci_dev_get(dev);
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break;
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case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
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cs5530_0 = pci_dev_get(dev);
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break;
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}
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}
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if (!master_0) {
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printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
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goto out;
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}
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if (!cs5530_0) {
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printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
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goto out;
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}
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/*
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* Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
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* --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
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*/
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pci_set_master(cs5530_0);
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pci_try_set_mwi(cs5530_0);
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/*
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* Set PCI CacheLineSize to 16-bytes:
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* --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
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*/
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pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
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/*
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* Disable trapping of UDMA register accesses (Win98 hack):
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* --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
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*/
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pci_write_config_word(cs5530_0, 0xd0, 0x5006);
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/*
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* Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
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* The other settings are what is necessary to get the register
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* into a sane state for IDE DMA operation.
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*/
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pci_write_config_byte(master_0, 0x40, 0x1e);
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/*
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* Set max PCI burst size (16-bytes seems to work best):
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* 16bytes: set bit-1 at 0x41 (reg value of 0x16)
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* all others: clear bit-1 at 0x41, and do:
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* 128bytes: OR 0x00 at 0x41
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* 256bytes: OR 0x04 at 0x41
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* 512bytes: OR 0x08 at 0x41
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* 1024bytes: OR 0x0c at 0x41
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*/
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pci_write_config_byte(master_0, 0x41, 0x14);
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/*
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* These settings are necessary to get the chip
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* into a sane state for IDE DMA operation.
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*/
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pci_write_config_byte(master_0, 0x42, 0x00);
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pci_write_config_byte(master_0, 0x43, 0xc1);
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out:
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pci_dev_put(master_0);
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pci_dev_put(cs5530_0);
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return 0;
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}
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/**
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* init_hwif_cs5530 - initialise an IDE channel
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* @hwif: IDE to initialize
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*
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* This gets invoked by the IDE driver once for each channel. It
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* performs channel-specific pre-initialization before drive probing.
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*/
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static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
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{
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unsigned long basereg;
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u32 d0_timings;
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basereg = CS5530_BASEREG(hwif);
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d0_timings = inl(basereg + 0);
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if (CS5530_BAD_PIO(d0_timings))
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outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
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if (CS5530_BAD_PIO(inl(basereg + 8)))
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outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
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}
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static const struct ide_port_ops cs5530_port_ops = {
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.set_pio_mode = cs5530_set_pio_mode,
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.set_dma_mode = cs5530_set_dma_mode,
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.udma_filter = cs5530_udma_filter,
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};
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static const struct ide_port_info cs5530_chipset __devinitdata = {
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.name = DRV_NAME,
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.init_chipset = init_chipset_cs5530,
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.init_hwif = init_hwif_cs5530,
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.port_ops = &cs5530_port_ops,
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.host_flags = IDE_HFLAG_SERIALIZE |
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IDE_HFLAG_POST_SET_MODE,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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};
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static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_pci_init_one(dev, &cs5530_chipset, NULL);
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}
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static const struct pci_device_id cs5530_pci_tbl[] = {
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{ PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
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static struct pci_driver cs5530_pci_driver = {
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.name = "CS5530 IDE",
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.id_table = cs5530_pci_tbl,
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.probe = cs5530_init_one,
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.remove = ide_pci_remove,
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.suspend = ide_pci_suspend,
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.resume = ide_pci_resume,
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};
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static int __init cs5530_ide_init(void)
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{
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return ide_pci_register_driver(&cs5530_pci_driver);
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}
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static void __exit cs5530_ide_exit(void)
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{
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pci_unregister_driver(&cs5530_pci_driver);
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}
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module_init(cs5530_ide_init);
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module_exit(cs5530_ide_exit);
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MODULE_AUTHOR("Mark Lord");
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MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
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MODULE_LICENSE("GPL");
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