231 lines
6.8 KiB
C
231 lines
6.8 KiB
C
/*
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* Driver for the NXP ISP1760 chip
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*
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* Copyright 2014 Laurent Pinchart
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* Copyright 2007 Sebastian Siewior
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*
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* Contacts:
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* Sebastian Siewior <bigeasy@linutronix.de>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*/
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#ifndef _ISP1760_REGS_H_
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#define _ISP1760_REGS_H_
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/* -----------------------------------------------------------------------------
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* Host Controller
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*/
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/* EHCI capability registers */
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#define HC_CAPLENGTH 0x000
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#define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */
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#define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */
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#define HC_HCSPARAMS 0x004
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#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */
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#define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */
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#define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */
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#define HC_HCCPARAMS 0x008
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#define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */
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#define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */
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/* EHCI operational registers */
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#define HC_USBCMD 0x020
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#define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */
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#define CMD_RESET (1 << 1) /* reset HC not bus */
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#define CMD_RUN (1 << 0) /* start/stop HC */
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#define HC_USBSTS 0x024
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#define STS_PCD (1 << 2) /* port change detect */
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#define HC_FRINDEX 0x02c
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#define HC_CONFIGFLAG 0x060
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#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
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#define HC_PORTSC1 0x064
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#define PORT_OWNER (1 << 13) /* true: companion hc owns this port */
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#define PORT_POWER (1 << 12) /* true: has power (see PPC) */
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#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
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#define PORT_RESET (1 << 8) /* reset port */
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#define PORT_SUSPEND (1 << 7) /* suspend port */
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#define PORT_RESUME (1 << 6) /* resume it */
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#define PORT_PE (1 << 2) /* port enable */
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#define PORT_CSC (1 << 1) /* connect status change */
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#define PORT_CONNECT (1 << 0) /* device connected */
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#define PORT_RWC_BITS (PORT_CSC)
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#define HC_ISO_PTD_DONEMAP_REG 0x130
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#define HC_ISO_PTD_SKIPMAP_REG 0x134
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#define HC_ISO_PTD_LASTPTD_REG 0x138
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#define HC_INT_PTD_DONEMAP_REG 0x140
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#define HC_INT_PTD_SKIPMAP_REG 0x144
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#define HC_INT_PTD_LASTPTD_REG 0x148
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#define HC_ATL_PTD_DONEMAP_REG 0x150
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#define HC_ATL_PTD_SKIPMAP_REG 0x154
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#define HC_ATL_PTD_LASTPTD_REG 0x158
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/* Configuration Register */
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#define HC_HW_MODE_CTRL 0x300
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#define ALL_ATX_RESET (1 << 31)
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#define HW_ANA_DIGI_OC (1 << 15)
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#define HW_DEV_DMA (1 << 11)
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#define HW_COMN_IRQ (1 << 10)
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#define HW_COMN_DMA (1 << 9)
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#define HW_DATA_BUS_32BIT (1 << 8)
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#define HW_DACK_POL_HIGH (1 << 6)
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#define HW_DREQ_POL_HIGH (1 << 5)
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#define HW_INTR_HIGH_ACT (1 << 2)
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#define HW_INTR_EDGE_TRIG (1 << 1)
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#define HW_GLOBAL_INTR_EN (1 << 0)
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#define HC_CHIP_ID_REG 0x304
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#define HC_SCRATCH_REG 0x308
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#define HC_RESET_REG 0x30c
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#define SW_RESET_RESET_HC (1 << 1)
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#define SW_RESET_RESET_ALL (1 << 0)
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#define HC_BUFFER_STATUS_REG 0x334
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#define ISO_BUF_FILL (1 << 2)
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#define INT_BUF_FILL (1 << 1)
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#define ATL_BUF_FILL (1 << 0)
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#define HC_MEMORY_REG 0x33c
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#define ISP_BANK(x) ((x) << 16)
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#define HC_PORT1_CTRL 0x374
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#define PORT1_POWER (3 << 3)
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#define PORT1_INIT1 (1 << 7)
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#define PORT1_INIT2 (1 << 23)
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#define HW_OTG_CTRL_SET 0x374
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#define HW_OTG_CTRL_CLR 0x376
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#define HW_OTG_DISABLE (1 << 10)
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#define HW_OTG_SE0_EN (1 << 9)
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#define HW_BDIS_ACON_EN (1 << 8)
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#define HW_SW_SEL_HC_DC (1 << 7)
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#define HW_VBUS_CHRG (1 << 6)
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#define HW_VBUS_DISCHRG (1 << 5)
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#define HW_VBUS_DRV (1 << 4)
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#define HW_SEL_CP_EXT (1 << 3)
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#define HW_DM_PULLDOWN (1 << 2)
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#define HW_DP_PULLDOWN (1 << 1)
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#define HW_DP_PULLUP (1 << 0)
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/* Interrupt Register */
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#define HC_INTERRUPT_REG 0x310
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#define HC_INTERRUPT_ENABLE 0x314
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#define HC_ISO_INT (1 << 9)
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#define HC_ATL_INT (1 << 8)
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#define HC_INTL_INT (1 << 7)
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#define HC_EOT_INT (1 << 3)
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#define HC_SOT_INT (1 << 1)
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#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
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#define HC_ISO_IRQ_MASK_OR_REG 0x318
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#define HC_INT_IRQ_MASK_OR_REG 0x31c
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#define HC_ATL_IRQ_MASK_OR_REG 0x320
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#define HC_ISO_IRQ_MASK_AND_REG 0x324
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#define HC_INT_IRQ_MASK_AND_REG 0x328
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#define HC_ATL_IRQ_MASK_AND_REG 0x32c
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/* -----------------------------------------------------------------------------
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* Peripheral Controller
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*/
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/* Initialization Registers */
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#define DC_ADDRESS 0x0200
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#define DC_DEVEN (1 << 7)
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#define DC_MODE 0x020c
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#define DC_DMACLKON (1 << 9)
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#define DC_VBUSSTAT (1 << 8)
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#define DC_CLKAON (1 << 7)
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#define DC_SNDRSU (1 << 6)
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#define DC_GOSUSP (1 << 5)
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#define DC_SFRESET (1 << 4)
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#define DC_GLINTENA (1 << 3)
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#define DC_WKUPCS (1 << 2)
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#define DC_INTCONF 0x0210
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#define DC_CDBGMOD_ACK_NAK (0 << 6)
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#define DC_CDBGMOD_ACK (1 << 6)
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#define DC_CDBGMOD_ACK_1NAK (2 << 6)
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#define DC_DDBGMODIN_ACK_NAK (0 << 4)
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#define DC_DDBGMODIN_ACK (1 << 4)
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#define DC_DDBGMODIN_ACK_1NAK (2 << 4)
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#define DC_DDBGMODOUT_ACK_NYET_NAK (0 << 2)
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#define DC_DDBGMODOUT_ACK_NYET (1 << 2)
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#define DC_DDBGMODOUT_ACK_NYET_1NAK (2 << 2)
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#define DC_INTLVL (1 << 1)
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#define DC_INTPOL (1 << 0)
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#define DC_DEBUG 0x0212
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#define DC_INTENABLE 0x0214
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#define DC_IEPTX(n) (1 << (11 + 2 * (n)))
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#define DC_IEPRX(n) (1 << (10 + 2 * (n)))
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#define DC_IEPRXTX(n) (3 << (10 + 2 * (n)))
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#define DC_IEP0SETUP (1 << 8)
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#define DC_IEVBUS (1 << 7)
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#define DC_IEDMA (1 << 6)
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#define DC_IEHS_STA (1 << 5)
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#define DC_IERESM (1 << 4)
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#define DC_IESUSP (1 << 3)
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#define DC_IEPSOF (1 << 2)
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#define DC_IESOF (1 << 1)
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#define DC_IEBRST (1 << 0)
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/* Data Flow Registers */
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#define DC_EPINDEX 0x022c
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#define DC_EP0SETUP (1 << 5)
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#define DC_ENDPIDX(n) ((n) << 1)
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#define DC_EPDIR (1 << 0)
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#define DC_CTRLFUNC 0x0228
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#define DC_CLBUF (1 << 4)
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#define DC_VENDP (1 << 3)
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#define DC_DSEN (1 << 2)
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#define DC_STATUS (1 << 1)
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#define DC_STALL (1 << 0)
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#define DC_DATAPORT 0x0220
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#define DC_BUFLEN 0x021c
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#define DC_DATACOUNT_MASK 0xffff
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#define DC_BUFSTAT 0x021e
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#define DC_EPMAXPKTSZ 0x0204
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#define DC_EPTYPE 0x0208
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#define DC_NOEMPKT (1 << 4)
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#define DC_EPENABLE (1 << 3)
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#define DC_DBLBUF (1 << 2)
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#define DC_ENDPTYP_ISOC (1 << 0)
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#define DC_ENDPTYP_BULK (2 << 0)
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#define DC_ENDPTYP_INTERRUPT (3 << 0)
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/* DMA Registers */
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#define DC_DMACMD 0x0230
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#define DC_DMATXCOUNT 0x0234
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#define DC_DMACONF 0x0238
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#define DC_DMAHW 0x023c
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#define DC_DMAINTREASON 0x0250
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#define DC_DMAINTEN 0x0254
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#define DC_DMAEP 0x0258
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#define DC_DMABURSTCOUNT 0x0264
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/* General Registers */
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#define DC_INTERRUPT 0x0218
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#define DC_CHIPID 0x0270
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#define DC_FRAMENUM 0x0274
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#define DC_SCRATCH 0x0278
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#define DC_UNLOCKDEV 0x027c
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#define DC_INTPULSEWIDTH 0x0280
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#define DC_TESTMODE 0x0284
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#endif
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