364 lines
10 KiB
Plaintext
364 lines
10 KiB
Plaintext
/*
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* phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
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*
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* Copyright 2006 Pengutronix
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* Sascha Hauer <s.hauer@pengutronix.de>
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* Copyright 2007 Pengutronix
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* Juergen Beisert <j.beisert@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "phytec,pcm030";
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compatible = "phytec,pcm030";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,5200@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <0x4000>; /* L1, 16K */
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i-cache-size = <0x4000>; /* L1, 16K */
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timebase-frequency = <0>; /* From Bootloader */
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bus-frequency = <0>; /* From Bootloader */
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clock-frequency = <0>; /* From Bootloader */
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x04000000>; /* 64MB */
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};
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soc5200@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc5200b-immr";
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ranges = <0x0 0xf0000000 0x0000c000>;
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bus-frequency = <0>; /* From bootloader */
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system-frequency = <0>; /* From bootloader */
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cdm@200 {
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compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
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reg = <0x200 0x38>;
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};
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mpc5200_pic: interrupt-controller@500 {
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/* 5200 interrupts are encoded into two levels; */
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interrupt-controller;
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#interrupt-cells = <3>;
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device_type = "interrupt-controller";
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compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
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reg = <0x500 0x80>;
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};
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timer@600 { /* General Purpose Timer */
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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cell-index = <0>;
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reg = <0x600 0x10>;
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interrupts = <0x1 0x9 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl,has-wdt;
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};
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timer@610 { /* General Purpose Timer */
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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cell-index = <1>;
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reg = <0x610 0x10>;
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interrupts = <0x1 0xa 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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gpt2: timer@620 { /* General Purpose Timer in GPIO mode */
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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cell-index = <2>;
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reg = <0x620 0x10>;
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interrupts = <0x1 0xb 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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cell-index = <3>;
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reg = <0x630 0x10>;
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interrupts = <0x1 0xc 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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cell-index = <4>;
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reg = <0x640 0x10>;
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interrupts = <0x1 0xd 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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cell-index = <5>;
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reg = <0x650 0x10>;
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interrupts = <0x1 0xe 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt6: timer@660 { /* General Purpose Timer in GPIO mode */
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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cell-index = <6>;
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reg = <0x660 0x10>;
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interrupts = <0x1 0xf 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpt7: timer@670 { /* General Purpose Timer in GPIO mode */
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compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
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cell-index = <7>;
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reg = <0x670 0x10>;
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interrupts = <0x1 0x10 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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rtc@800 { // Real time clock
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compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
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device_type = "rtc";
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reg = <0x800 0x100>;
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interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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can@900 {
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compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
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cell-index = <0>;
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interrupts = <0x2 0x11 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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reg = <0x900 0x80>;
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};
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can@980 {
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compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
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cell-index = <1>;
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interrupts = <0x2 0x12 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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reg = <0x980 0x80>;
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};
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gpio_simple: gpio@b00 {
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compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
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reg = <0xb00 0x40>;
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interrupts = <0x1 0x7 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio_wkup: gpio-wkup@c00 {
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compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
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reg = <0xc00 0x40>;
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interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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spi@f00 {
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compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
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reg = <0xf00 0x20>;
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interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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usb@1000 {
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compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
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reg = <0x1000 0xff>;
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interrupts = <0x2 0x6 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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dma-controller@1200 {
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device_type = "dma-controller";
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compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
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reg = <0x1200 0x80>;
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interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0
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0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0
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0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0
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0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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xlb@1f00 {
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compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
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reg = <0x1f00 0x100>;
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};
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ac97@2000 { /* PSC1 in ac97 mode */
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device_type = "sound";
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compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
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cell-index = <0>;
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reg = <0x2000 0x100>;
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interrupts = <0x2 0x2 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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/* PSC2 port is used by CAN1/2 */
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serial@2400 { /* PSC3 in UART mode */
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device_type = "serial";
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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port-number = <0>;
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cell-index = <2>;
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reg = <0x2400 0x100>;
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interrupts = <0x2 0x3 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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/* PSC4 is ??? */
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/* PSC5 is ??? */
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serial@2c00 { /* PSC6 in UART mode */
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device_type = "serial";
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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port-number = <1>;
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cell-index = <5>;
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reg = <0x2c00 0x100>;
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interrupts = <0x2 0x4 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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ethernet@3000 {
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device_type = "network";
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compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
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reg = <0x3000 0x400>;
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local-mac-address = [00 00 00 00 00 00];
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interrupts = <0x2 0x5 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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phy-handle = <&phy0>;
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};
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mdio@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
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reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */
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interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */
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interrupt-parent = <&mpc5200_pic>;
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phy0:ethernet-phy@0 {
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device_type = "ethernet-phy";
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reg = <0x0>;
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};
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};
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ata@3a00 {
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device_type = "ata";
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compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
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reg = <0x3a00 0x100>;
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interrupts = <0x2 0x7 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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i2c@3d00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
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cell-index = <0>;
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reg = <0x3d00 0x40>;
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interrupts = <0x2 0xf 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl5200-clocking;
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};
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i2c@3d40 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
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cell-index = <1>;
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reg = <0x3d40 0x40>;
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interrupts = <0x2 0x10 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl5200-clocking;
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rtc@51 {
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device_type = "rtc";
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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/* FIXME: EEPROM */
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};
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sram@8000 {
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compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
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reg = <0x8000 0x4000>;
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};
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/* This is only an example device to show the usage of gpios. It maps all available
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* gpios to the "gpio-provider" device.
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*/
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gpio {
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compatible = "gpio-provider";
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/* mpc52xx exp.con patchfield */
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gpios = <&gpio_wkup 0 0 /* GPIO_WKUP_7 11d jp13-3 */
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&gpio_wkup 1 0 /* GPIO_WKUP_6 14c */
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&gpio_wkup 6 0 /* PSC2_4 43c x5-11 */
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&gpio_simple 2 0 /* IRDA_1 24c x7-6 set GPS_PORT_CONFIG[IRDA] = 0 */
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&gpio_simple 3 0 /* IRDA_0 x8-5 set GPS_PORT_CONFIG[IRDA] = 0 */
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&gpt2 0 0 /* timer2 12d x4-4 */
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&gpt3 0 0 /* timer3 13d x6-4 */
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&gpt4 0 0 /* timer4 61c x2-16 */
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&gpt5 0 0 /* timer5 44c x7-11 */
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&gpt6 0 0 /* timer6 60c x8-15 */
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&gpt7 0 0 /* timer7 36a x17-9 */
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>;
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};
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};
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pci@f0000d00 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
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reg = <0xf0000d00 0x100>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */
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0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3
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0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3
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0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3
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0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */
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0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3
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0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3
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0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>;
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clock-frequency = <0>; // From boot loader
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interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>;
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interrupt-parent = <&mpc5200_pic>;
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bus-range = <0 0>;
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ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>;
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};
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};
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