2014 lines
65 KiB
C
2014 lines
65 KiB
C
/*
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* Allwinner A1X SoCs pinctrl driver.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "core.h"
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun4i_a10_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ERXD3 */
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SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
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SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ERXD2 */
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SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
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SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ERXD1 */
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SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
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SUNXI_FUNCTION(0x4, "uart2")), /* TX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ERXD0 */
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SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
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SUNXI_FUNCTION(0x4, "uart2")), /* RX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ETXD3 */
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SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ETXD2 */
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SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ETXD1 */
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SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ETXD0 */
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SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ERXCK */
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SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ERXERR */
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SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ERXDV */
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SUNXI_FUNCTION(0x4, "uart1")), /* TX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* EMDC */
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SUNXI_FUNCTION(0x4, "uart1")), /* RX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* EMDIO */
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SUNXI_FUNCTION(0x3, "uart6"), /* TX */
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SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ETXEN */
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SUNXI_FUNCTION(0x3, "uart6"), /* RX */
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SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ETXCK */
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SUNXI_FUNCTION(0x3, "uart7"), /* TX */
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SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ECRS */
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SUNXI_FUNCTION(0x3, "uart7"), /* RX */
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SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ECOL */
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SUNXI_FUNCTION(0x3, "can"), /* TX */
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SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "wemac"), /* ETXERR */
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SUNXI_FUNCTION(0x3, "can"), /* RX */
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SUNXI_FUNCTION(0x4, "uart1")), /* RING */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "ir0")), /* TX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "ir0")), /* RX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
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SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
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SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
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SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
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SUNXI_FUNCTION(0x3, "ac97")), /* DO */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s"), /* DI */
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SUNXI_FUNCTION(0x3, "ac97")), /* DI */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
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SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
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SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
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SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
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SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart0"), /* TX */
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SUNXI_FUNCTION(0x3, "ir1")), /* TX */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart0"), /* RX */
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SUNXI_FUNCTION(0x3, "ir1")), /* RX */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
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SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
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SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
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SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
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SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
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SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
|
|
SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
|
|
SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
|
|
SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
|
|
SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
|
|
SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
|
|
SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
|
|
SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
|
|
SUNXI_FUNCTION(0x3, "sim")), /* DET */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
|
|
SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
|
|
SUNXI_FUNCTION(0x3, "sim")), /* RST */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
|
|
SUNXI_FUNCTION(0x3, "sim")), /* SCK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
|
|
SUNXI_FUNCTION(0x3, "sim")), /* SDA */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* CK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
|
|
SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
|
|
SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
|
|
SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
|
|
SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
|
|
SUNXI_FUNCTION(0x4, "uart0")), /* TX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
|
|
SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
|
|
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
|
|
SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
|
|
SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* CK */
|
|
SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
|
|
SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
|
|
SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
|
|
SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
|
|
SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
|
|
SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
|
|
SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
|
|
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
|
|
SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
|
|
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
|
|
SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
|
|
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
|
|
SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
|
|
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
|
|
SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
|
|
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
|
|
SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
|
|
SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
|
|
SUNXI_FUNCTION(0x4, "uart4"), /* RX */
|
|
SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
|
|
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
|
|
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
|
|
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
|
|
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
|
|
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
|
|
SUNXI_FUNCTION(0x4, "uart4"), /* RX */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
|
|
SUNXI_FUNCTION(0x4, "uart5"), /* TX */
|
|
SUNXI_FUNCTION(0x5, "ms"), /* BS */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
|
|
SUNXI_FUNCTION(0x4, "uart5"), /* RX */
|
|
SUNXI_FUNCTION(0x5, "ms"), /* CLK */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
|
|
SUNXI_FUNCTION(0x5, "ms"), /* D0 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
|
|
SUNXI_FUNCTION(0x5, "ms"), /* D1 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
|
|
SUNXI_FUNCTION(0x5, "ms"), /* D2 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
|
|
SUNXI_FUNCTION(0x5, "ms"), /* D3 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
|
|
SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
|
|
SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
|
|
SUNXI_FUNCTION(0x5, "sim"), /* RST */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
|
|
SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
|
|
SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
|
|
SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
|
|
SUNXI_FUNCTION(0x5, "sim"), /* SCK */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
|
|
SUNXI_FUNCTION(0x5, "sim"), /* SDA */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
|
|
SUNXI_FUNCTION(0x4, "can"), /* TX */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
|
|
SUNXI_FUNCTION(0x4, "can"), /* RX */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
|
|
SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
|
|
SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
|
|
SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
|
|
SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
|
|
SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
|
|
SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
|
|
SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
|
|
SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
|
|
SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
|
|
SUNXI_FUNCTION(0x3, "uart5")), /* TX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
|
|
SUNXI_FUNCTION(0x3, "uart5")), /* RX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
|
|
SUNXI_FUNCTION(0x3, "uart6")), /* TX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
|
|
SUNXI_FUNCTION(0x3, "uart6")), /* RX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
|
|
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
|
|
SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
|
|
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
|
|
SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
|
|
SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
|
|
SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
|
|
SUNXI_FUNCTION(0x3, "uart2")), /* TX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
|
|
SUNXI_FUNCTION(0x3, "uart2")), /* RX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
|
|
SUNXI_FUNCTION(0x3, "uart7"), /* TX */
|
|
SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
|
|
SUNXI_FUNCTION(0x3, "uart7"), /* RX */
|
|
SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
|
|
};
|
|
|
|
static const struct sunxi_desc_pin sun5i_a13_pins[] = {
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "pwm")),
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ir0")), /* TX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "ir0")), /* RX */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
|
|
SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
|
|
SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
|
|
SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
|
|
SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
|
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
|
|
SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
|
|
SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
|
|
SUNXI_FUNCTION(0x4, "spi2")), /* CLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
|
|
SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
|
|
SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
|
|
SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
|
|
SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
|
|
SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
|
|
SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
|
|
SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
|
|
SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
|
|
SUNXI_FUNCTION(0x4, "uart1")), /* TX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
|
|
SUNXI_FUNCTION(0x4, "uart1")), /* RX */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out")),
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
|
|
SUNXI_FUNCTION(0x4, "uart1")), /* TX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
|
|
SUNXI_FUNCTION(0x4, "uart1")), /* RX */
|
|
/* Hole */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
|
|
SUNXI_FUNCTION(0x3, "uart3")), /* TX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
|
|
SUNXI_FUNCTION(0x3, "uart3")), /* RX */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
|
|
SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
|
|
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
|
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
|
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
|
|
SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
|
|
.pins = sun4i_a10_pins,
|
|
.npins = ARRAY_SIZE(sun4i_a10_pins),
|
|
};
|
|
|
|
static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
|
|
.pins = sun5i_a13_pins,
|
|
.npins = ARRAY_SIZE(sun5i_a13_pins),
|
|
};
|
|
|
|
static struct sunxi_pinctrl_group *
|
|
sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < pctl->ngroups; i++) {
|
|
struct sunxi_pinctrl_group *grp = pctl->groups + i;
|
|
|
|
if (!strcmp(grp->name, group))
|
|
return grp;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static struct sunxi_pinctrl_function *
|
|
sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
|
|
const char *name)
|
|
{
|
|
struct sunxi_pinctrl_function *func = pctl->functions;
|
|
int i;
|
|
|
|
for (i = 0; i < pctl->nfunctions; i++) {
|
|
if (!func[i].name)
|
|
break;
|
|
|
|
if (!strcmp(func[i].name, name))
|
|
return func + i;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static struct sunxi_desc_function *
|
|
sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
|
|
const char *pin_name,
|
|
const char *func_name)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
|
|
if (!strcmp(pin->pin.name, pin_name)) {
|
|
struct sunxi_desc_function *func = pin->functions;
|
|
|
|
while (func->name) {
|
|
if (!strcmp(func->name, func_name))
|
|
return func;
|
|
|
|
func++;
|
|
}
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pctl->ngroups;
|
|
}
|
|
|
|
static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
|
|
unsigned group)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pctl->groups[group].name;
|
|
}
|
|
|
|
static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
|
|
unsigned group,
|
|
const unsigned **pins,
|
|
unsigned *num_pins)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
*pins = (unsigned *)&pctl->groups[group].pin;
|
|
*num_pins = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
|
struct device_node *node,
|
|
struct pinctrl_map **map,
|
|
unsigned *num_maps)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
unsigned long *pinconfig;
|
|
struct property *prop;
|
|
const char *function;
|
|
const char *group;
|
|
int ret, nmaps, i = 0;
|
|
u32 val;
|
|
|
|
*map = NULL;
|
|
*num_maps = 0;
|
|
|
|
ret = of_property_read_string(node, "allwinner,function", &function);
|
|
if (ret) {
|
|
dev_err(pctl->dev,
|
|
"missing allwinner,function property in node %s\n",
|
|
node->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
|
|
if (nmaps < 0) {
|
|
dev_err(pctl->dev,
|
|
"missing allwinner,pins property in node %s\n",
|
|
node->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
|
|
if (!map)
|
|
return -ENOMEM;
|
|
|
|
of_property_for_each_string(node, "allwinner,pins", prop, group) {
|
|
struct sunxi_pinctrl_group *grp =
|
|
sunxi_pinctrl_find_group_by_name(pctl, group);
|
|
int j = 0, configlen = 0;
|
|
|
|
if (!grp) {
|
|
dev_err(pctl->dev, "unknown pin %s", group);
|
|
continue;
|
|
}
|
|
|
|
if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
|
|
grp->name,
|
|
function)) {
|
|
dev_err(pctl->dev, "unsupported function %s on pin %s",
|
|
function, group);
|
|
continue;
|
|
}
|
|
|
|
(*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
|
|
(*map)[i].data.mux.group = group;
|
|
(*map)[i].data.mux.function = function;
|
|
|
|
i++;
|
|
|
|
(*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
|
|
(*map)[i].data.configs.group_or_pin = group;
|
|
|
|
if (of_find_property(node, "allwinner,drive", NULL))
|
|
configlen++;
|
|
if (of_find_property(node, "allwinner,pull", NULL))
|
|
configlen++;
|
|
|
|
pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
|
|
|
|
if (!of_property_read_u32(node, "allwinner,drive", &val)) {
|
|
u16 strength = (val + 1) * 10;
|
|
pinconfig[j++] =
|
|
pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
|
|
strength);
|
|
}
|
|
|
|
if (!of_property_read_u32(node, "allwinner,pull", &val)) {
|
|
enum pin_config_param pull = PIN_CONFIG_END;
|
|
if (val == 1)
|
|
pull = PIN_CONFIG_BIAS_PULL_UP;
|
|
else if (val == 2)
|
|
pull = PIN_CONFIG_BIAS_PULL_DOWN;
|
|
pinconfig[j++] = pinconf_to_config_packed(pull, 0);
|
|
}
|
|
|
|
(*map)[i].data.configs.configs = pinconfig;
|
|
(*map)[i].data.configs.num_configs = configlen;
|
|
|
|
i++;
|
|
}
|
|
|
|
*num_maps = nmaps;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
|
|
struct pinctrl_map *map,
|
|
unsigned num_maps)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < num_maps; i++) {
|
|
if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
|
|
kfree(map[i].data.configs.configs);
|
|
}
|
|
|
|
kfree(map);
|
|
}
|
|
|
|
static const struct pinctrl_ops sunxi_pctrl_ops = {
|
|
.dt_node_to_map = sunxi_pctrl_dt_node_to_map,
|
|
.dt_free_map = sunxi_pctrl_dt_free_map,
|
|
.get_groups_count = sunxi_pctrl_get_groups_count,
|
|
.get_group_name = sunxi_pctrl_get_group_name,
|
|
.get_group_pins = sunxi_pctrl_get_group_pins,
|
|
};
|
|
|
|
static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
|
|
unsigned group,
|
|
unsigned long *config)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
*config = pctl->groups[group].config;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
|
|
unsigned group,
|
|
unsigned long config)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
struct sunxi_pinctrl_group *g = &pctl->groups[group];
|
|
u32 val, mask;
|
|
u16 strength;
|
|
u8 dlevel;
|
|
|
|
switch (pinconf_to_config_param(config)) {
|
|
case PIN_CONFIG_DRIVE_STRENGTH:
|
|
strength = pinconf_to_config_argument(config);
|
|
if (strength > 40)
|
|
return -EINVAL;
|
|
/*
|
|
* We convert from mA to what the register expects:
|
|
* 0: 10mA
|
|
* 1: 20mA
|
|
* 2: 30mA
|
|
* 3: 40mA
|
|
*/
|
|
dlevel = strength / 10 - 1;
|
|
val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
|
|
mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
|
|
writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),
|
|
pctl->membase + sunxi_dlevel_reg(g->pin));
|
|
break;
|
|
case PIN_CONFIG_BIAS_PULL_UP:
|
|
val = readl(pctl->membase + sunxi_pull_reg(g->pin));
|
|
mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
|
|
writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
|
|
pctl->membase + sunxi_pull_reg(g->pin));
|
|
break;
|
|
case PIN_CONFIG_BIAS_PULL_DOWN:
|
|
val = readl(pctl->membase + sunxi_pull_reg(g->pin));
|
|
mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
|
|
writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
|
|
pctl->membase + sunxi_pull_reg(g->pin));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* cache the config value */
|
|
g->config = config;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pinconf_ops sunxi_pconf_ops = {
|
|
.pin_config_group_get = sunxi_pconf_group_get,
|
|
.pin_config_group_set = sunxi_pconf_group_set,
|
|
};
|
|
|
|
static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pctl->nfunctions;
|
|
}
|
|
|
|
static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
|
|
unsigned function)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
return pctl->functions[function].name;
|
|
}
|
|
|
|
static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
|
|
unsigned function,
|
|
const char * const **groups,
|
|
unsigned * const num_groups)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
*groups = pctl->functions[function].groups;
|
|
*num_groups = pctl->functions[function].ngroups;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
|
|
unsigned pin,
|
|
u8 config)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
|
|
u32 val = readl(pctl->membase + sunxi_mux_reg(pin));
|
|
u32 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
|
|
writel((val & ~mask) | config << sunxi_mux_offset(pin),
|
|
pctl->membase + sunxi_mux_reg(pin));
|
|
}
|
|
|
|
static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
|
|
unsigned function,
|
|
unsigned group)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
struct sunxi_pinctrl_group *g = pctl->groups + group;
|
|
struct sunxi_pinctrl_function *func = pctl->functions + function;
|
|
struct sunxi_desc_function *desc =
|
|
sunxi_pinctrl_desc_find_function_by_name(pctl,
|
|
g->name,
|
|
func->name);
|
|
|
|
if (!desc)
|
|
return -EINVAL;
|
|
|
|
sunxi_pmx_set(pctldev, g->pin, desc->muxval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
|
struct pinctrl_gpio_range *range,
|
|
unsigned offset,
|
|
bool input)
|
|
{
|
|
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
|
struct sunxi_desc_function *desc;
|
|
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
|
|
const char *func;
|
|
u8 bank, pin;
|
|
int ret;
|
|
|
|
bank = (offset) / PINS_PER_BANK;
|
|
pin = (offset) % PINS_PER_BANK;
|
|
|
|
ret = sprintf(pin_name, "P%c%d", 'A' + bank, pin);
|
|
if (!ret)
|
|
goto error;
|
|
|
|
if (input)
|
|
func = "gpio_in";
|
|
else
|
|
func = "gpio_out";
|
|
|
|
desc = sunxi_pinctrl_desc_find_function_by_name(pctl,
|
|
pin_name,
|
|
func);
|
|
if (!desc) {
|
|
ret = -EINVAL;
|
|
goto error;
|
|
}
|
|
|
|
sunxi_pmx_set(pctldev, offset, desc->muxval);
|
|
|
|
ret = 0;
|
|
|
|
error:
|
|
return ret;
|
|
}
|
|
|
|
static const struct pinmux_ops sunxi_pmx_ops = {
|
|
.get_functions_count = sunxi_pmx_get_funcs_cnt,
|
|
.get_function_name = sunxi_pmx_get_func_name,
|
|
.get_function_groups = sunxi_pmx_get_func_groups,
|
|
.enable = sunxi_pmx_enable,
|
|
.gpio_set_direction = sunxi_pmx_gpio_set_direction,
|
|
};
|
|
|
|
static struct pinctrl_desc sunxi_pctrl_desc = {
|
|
.confops = &sunxi_pconf_ops,
|
|
.pctlops = &sunxi_pctrl_ops,
|
|
.pmxops = &sunxi_pmx_ops,
|
|
};
|
|
|
|
static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
return pinctrl_request_gpio(chip->base + offset);
|
|
}
|
|
|
|
static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
pinctrl_free_gpio(chip->base + offset);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
|
|
unsigned offset)
|
|
{
|
|
return pinctrl_gpio_direction_input(chip->base + offset);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
|
|
|
|
u32 reg = sunxi_data_reg(offset);
|
|
u8 index = sunxi_data_offset(offset);
|
|
u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
|
|
|
|
return val;
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
|
|
unsigned offset, int value)
|
|
{
|
|
return pinctrl_gpio_direction_output(chip->base + offset);
|
|
}
|
|
|
|
static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
|
|
unsigned offset, int value)
|
|
{
|
|
struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
|
|
u32 reg = sunxi_data_reg(offset);
|
|
u8 index = sunxi_data_offset(offset);
|
|
|
|
writel((value & DATA_PINS_MASK) << index, pctl->membase + reg);
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
|
|
const struct of_phandle_args *gpiospec,
|
|
u32 *flags)
|
|
{
|
|
int pin, base;
|
|
|
|
base = PINS_PER_BANK * gpiospec->args[0];
|
|
pin = base + gpiospec->args[1];
|
|
|
|
if (pin > (gc->base + gc->ngpio))
|
|
return -EINVAL;
|
|
|
|
if (flags)
|
|
*flags = gpiospec->args[2];
|
|
|
|
return pin;
|
|
}
|
|
|
|
static struct gpio_chip sunxi_pinctrl_gpio_chip = {
|
|
.owner = THIS_MODULE,
|
|
.request = sunxi_pinctrl_gpio_request,
|
|
.free = sunxi_pinctrl_gpio_free,
|
|
.direction_input = sunxi_pinctrl_gpio_direction_input,
|
|
.direction_output = sunxi_pinctrl_gpio_direction_output,
|
|
.get = sunxi_pinctrl_gpio_get,
|
|
.set = sunxi_pinctrl_gpio_set,
|
|
.of_xlate = sunxi_pinctrl_gpio_of_xlate,
|
|
.of_gpio_n_cells = 3,
|
|
.can_sleep = 0,
|
|
};
|
|
|
|
static struct of_device_id sunxi_pinctrl_match[] = {
|
|
{ .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
|
|
{ .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
|
|
|
|
static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
|
|
const char *name)
|
|
{
|
|
struct sunxi_pinctrl_function *func = pctl->functions;
|
|
|
|
while (func->name) {
|
|
/* function already there */
|
|
if (strcmp(func->name, name) == 0) {
|
|
func->ngroups++;
|
|
return -EEXIST;
|
|
}
|
|
func++;
|
|
}
|
|
|
|
func->name = name;
|
|
func->ngroups = 1;
|
|
|
|
pctl->nfunctions++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pinctrl_build_state(struct platform_device *pdev)
|
|
{
|
|
struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
pctl->ngroups = pctl->desc->npins;
|
|
|
|
/* Allocate groups */
|
|
pctl->groups = devm_kzalloc(&pdev->dev,
|
|
pctl->ngroups * sizeof(*pctl->groups),
|
|
GFP_KERNEL);
|
|
if (!pctl->groups)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_pinctrl_group *group = pctl->groups + i;
|
|
|
|
group->name = pin->pin.name;
|
|
group->pin = pin->pin.number;
|
|
}
|
|
|
|
/*
|
|
* We suppose that we won't have any more functions than pins,
|
|
* we'll reallocate that later anyway
|
|
*/
|
|
pctl->functions = devm_kzalloc(&pdev->dev,
|
|
pctl->desc->npins * sizeof(*pctl->functions),
|
|
GFP_KERNEL);
|
|
if (!pctl->functions)
|
|
return -ENOMEM;
|
|
|
|
/* Count functions and their associated groups */
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_desc_function *func = pin->functions;
|
|
|
|
while (func->name) {
|
|
sunxi_pinctrl_add_function(pctl, func->name);
|
|
func++;
|
|
}
|
|
}
|
|
|
|
pctl->functions = krealloc(pctl->functions,
|
|
pctl->nfunctions * sizeof(*pctl->functions),
|
|
GFP_KERNEL);
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_desc_function *func = pin->functions;
|
|
|
|
while (func->name) {
|
|
struct sunxi_pinctrl_function *func_item;
|
|
const char **func_grp;
|
|
|
|
func_item = sunxi_pinctrl_find_function_by_name(pctl,
|
|
func->name);
|
|
if (!func_item)
|
|
return -EINVAL;
|
|
|
|
if (!func_item->groups) {
|
|
func_item->groups =
|
|
devm_kzalloc(&pdev->dev,
|
|
func_item->ngroups * sizeof(*func_item->groups),
|
|
GFP_KERNEL);
|
|
if (!func_item->groups)
|
|
return -ENOMEM;
|
|
}
|
|
|
|
func_grp = func_item->groups;
|
|
while (*func_grp)
|
|
func_grp++;
|
|
|
|
*func_grp = pin->pin.name;
|
|
func++;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pinctrl_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
const struct of_device_id *device;
|
|
struct pinctrl_pin_desc *pins;
|
|
struct sunxi_pinctrl *pctl;
|
|
int i, ret, last_pin;
|
|
|
|
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
|
|
if (!pctl)
|
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, pctl);
|
|
|
|
pctl->membase = of_iomap(node, 0);
|
|
if (!pctl->membase)
|
|
return -ENOMEM;
|
|
|
|
device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
|
|
if (!device)
|
|
return -ENODEV;
|
|
|
|
pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
|
|
|
|
ret = sunxi_pinctrl_build_state(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pins = devm_kzalloc(&pdev->dev,
|
|
pctl->desc->npins * sizeof(*pins),
|
|
GFP_KERNEL);
|
|
if (!pins)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++)
|
|
pins[i] = pctl->desc->pins[i].pin;
|
|
|
|
sunxi_pctrl_desc.name = dev_name(&pdev->dev);
|
|
sunxi_pctrl_desc.owner = THIS_MODULE;
|
|
sunxi_pctrl_desc.pins = pins;
|
|
sunxi_pctrl_desc.npins = pctl->desc->npins;
|
|
pctl->dev = &pdev->dev;
|
|
pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
|
|
&pdev->dev, pctl);
|
|
if (!pctl->pctl_dev) {
|
|
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
|
|
if (!pctl->chip) {
|
|
ret = -ENOMEM;
|
|
goto pinctrl_error;
|
|
}
|
|
|
|
last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
|
|
pctl->chip = &sunxi_pinctrl_gpio_chip;
|
|
pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
|
|
pctl->chip->label = dev_name(&pdev->dev);
|
|
pctl->chip->dev = &pdev->dev;
|
|
pctl->chip->base = 0;
|
|
|
|
ret = gpiochip_add(pctl->chip);
|
|
if (ret)
|
|
goto pinctrl_error;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
|
|
ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
|
|
pin->pin.number,
|
|
pin->pin.number, 1);
|
|
if (ret)
|
|
goto gpiochip_error;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
|
|
|
|
return 0;
|
|
|
|
gpiochip_error:
|
|
ret = gpiochip_remove(pctl->chip);
|
|
pinctrl_error:
|
|
pinctrl_unregister(pctl->pctl_dev);
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver sunxi_pinctrl_driver = {
|
|
.probe = sunxi_pinctrl_probe,
|
|
.driver = {
|
|
.name = "sunxi-pinctrl",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = sunxi_pinctrl_match,
|
|
},
|
|
};
|
|
module_platform_driver(sunxi_pinctrl_driver);
|
|
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
|
|
MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
|
|
MODULE_LICENSE("GPL");
|