2de59fea8b
The PL310 on the ct-ca9x4 tile for the Versatile Express does not need to add additional latency when accessing its cache RAMs. Unfortunately, the boot monitor sets this up for an 8-cycle delay on reads and writes, resulting in greatly reduced memory performance when the L2 cache is enabled. This patch sets the L2 RAM latencies to the correct value of 1 cycle on the ct-ca9x4 tile before enabling the L2 cache. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
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| .. | ||
| include/mach | ||
| Kconfig | ||
| Makefile | ||
| Makefile.boot | ||
| core.h | ||
| ct-ca9x4.c | ||
| headsmp.S | ||
| localtimer.c | ||
| platsmp.c | ||
| v2m.c | ||