449 lines
10 KiB
C
449 lines
10 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License v2
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* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
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*
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* U5500 PRCM Unit interface driver
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/mutex.h>
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#include <linux/completion.h>
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#include <linux/irq.h>
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#include <linux/jiffies.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/db5500-prcmu.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include <mach/db5500-regs.h>
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#include "db5500-prcmu-regs.h"
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#define _PRCM_MB_HEADER (tcdm_base + 0xFE8)
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#define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
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#define PRCM_REQ_MB1_HEADER (_PRCM_MB_HEADER + 0x1)
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#define PRCM_REQ_MB2_HEADER (_PRCM_MB_HEADER + 0x2)
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#define PRCM_REQ_MB3_HEADER (_PRCM_MB_HEADER + 0x3)
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#define PRCM_REQ_MB4_HEADER (_PRCM_MB_HEADER + 0x4)
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#define PRCM_REQ_MB5_HEADER (_PRCM_MB_HEADER + 0x5)
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#define PRCM_REQ_MB6_HEADER (_PRCM_MB_HEADER + 0x6)
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#define PRCM_REQ_MB7_HEADER (_PRCM_MB_HEADER + 0x7)
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#define PRCM_ACK_MB0_HEADER (_PRCM_MB_HEADER + 0x8)
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#define PRCM_ACK_MB1_HEADER (_PRCM_MB_HEADER + 0x9)
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#define PRCM_ACK_MB2_HEADER (_PRCM_MB_HEADER + 0xa)
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#define PRCM_ACK_MB3_HEADER (_PRCM_MB_HEADER + 0xb)
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#define PRCM_ACK_MB4_HEADER (_PRCM_MB_HEADER + 0xc)
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#define PRCM_ACK_MB5_HEADER (_PRCM_MB_HEADER + 0xd)
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#define PRCM_ACK_MB6_HEADER (_PRCM_MB_HEADER + 0xe)
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#define PRCM_ACK_MB7_HEADER (_PRCM_MB_HEADER + 0xf)
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/* Req Mailboxes */
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#define PRCM_REQ_MB0 (tcdm_base + 0xFD8)
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#define PRCM_REQ_MB1 (tcdm_base + 0xFCC)
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#define PRCM_REQ_MB2 (tcdm_base + 0xFC4)
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#define PRCM_REQ_MB3 (tcdm_base + 0xFC0)
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#define PRCM_REQ_MB4 (tcdm_base + 0xF98)
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#define PRCM_REQ_MB5 (tcdm_base + 0xF90)
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#define PRCM_REQ_MB6 (tcdm_base + 0xF8C)
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#define PRCM_REQ_MB7 (tcdm_base + 0xF84)
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/* Ack Mailboxes */
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#define PRCM_ACK_MB0 (tcdm_base + 0xF38)
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#define PRCM_ACK_MB1 (tcdm_base + 0xF30)
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#define PRCM_ACK_MB2 (tcdm_base + 0xF24)
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#define PRCM_ACK_MB3 (tcdm_base + 0xF20)
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#define PRCM_ACK_MB4 (tcdm_base + 0xF1C)
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#define PRCM_ACK_MB5 (tcdm_base + 0xF14)
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#define PRCM_ACK_MB6 (tcdm_base + 0xF0C)
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#define PRCM_ACK_MB7 (tcdm_base + 0xF08)
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enum mb_return_code {
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RC_SUCCESS,
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RC_FAIL,
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};
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/* Mailbox 0 headers. */
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enum mb0_header {
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/* request */
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RMB0H_PWR_STATE_TRANS = 1,
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RMB0H_WAKE_UP_CFG,
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RMB0H_RD_WAKE_UP_ACK,
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/* acknowledge */
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AMB0H_WAKE_UP = 1,
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};
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/* Mailbox 5 headers. */
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enum mb5_header {
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MB5H_I2C_WRITE = 1,
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MB5H_I2C_READ,
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};
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/* Request mailbox 5 fields. */
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#define PRCM_REQ_MB5_I2C_SLAVE (PRCM_REQ_MB5 + 0)
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#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 1)
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#define PRCM_REQ_MB5_I2C_SIZE (PRCM_REQ_MB5 + 2)
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#define PRCM_REQ_MB5_I2C_DATA (PRCM_REQ_MB5 + 4)
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/* Acknowledge mailbox 5 fields. */
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#define PRCM_ACK_MB5_RETURN_CODE (PRCM_ACK_MB5 + 0)
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#define PRCM_ACK_MB5_I2C_DATA (PRCM_ACK_MB5 + 4)
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#define NUM_MB 8
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#define MBOX_BIT BIT
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#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
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/*
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* Used by MCDE to setup all necessary PRCMU registers
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*/
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#define PRCMU_RESET_DSIPLL 0x00004000
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#define PRCMU_UNCLAMP_DSIPLL 0x00400800
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/* HDMI CLK MGT PLLSW=001 (PLLSOC0), PLLDIV=0x8, = 50 Mhz*/
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#define PRCMU_DSI_CLOCK_SETTING 0x00000128
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/* TVCLK_MGT PLLSW=001 (PLLSOC0) PLLDIV=0x13, = 19.05 MHZ */
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#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000135
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#define PRCMU_PLLDSI_FREQ_SETTING 0x0004013C
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#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000002
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#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x03000101
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#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00000101
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#define PRCMU_ENABLE_PLLDSI 0x00000001
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#define PRCMU_DISABLE_PLLDSI 0x00000000
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#define PRCMU_DSI_RESET_SW 0x00000003
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#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
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/*
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* mb0_transfer - state needed for mailbox 0 communication.
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* @lock: The transaction lock.
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*/
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static struct {
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spinlock_t lock;
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} mb0_transfer;
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/*
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* mb5_transfer - state needed for mailbox 5 communication.
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* @lock: The transaction lock.
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* @work: The transaction completion structure.
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* @ack: Reply ("acknowledge") data.
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*/
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static struct {
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struct mutex lock;
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struct completion work;
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struct {
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u8 header;
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u8 status;
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u8 value[4];
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} ack;
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} mb5_transfer;
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/* PRCMU TCDM base IO address. */
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static __iomem void *tcdm_base;
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/**
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* db5500_prcmu_abb_read() - Read register value(s) from the ABB.
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* @slave: The I2C slave address.
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* @reg: The (start) register address.
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* @value: The read out value(s).
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* @size: The number of registers to read.
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*
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* Reads register value(s) from the ABB.
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* @size has to be <= 4.
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*/
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int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
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{
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int r;
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if ((size < 1) || (4 < size))
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return -EINVAL;
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mutex_lock(&mb5_transfer.lock);
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
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cpu_relax();
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writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
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writeb(reg, PRCM_REQ_MB5_I2C_REG);
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writeb(size, PRCM_REQ_MB5_I2C_SIZE);
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writeb(MB5H_I2C_READ, PRCM_REQ_MB5_HEADER);
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writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
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wait_for_completion(&mb5_transfer.work);
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r = 0;
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if ((mb5_transfer.ack.header == MB5H_I2C_READ) &&
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(mb5_transfer.ack.status == RC_SUCCESS))
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memcpy(value, mb5_transfer.ack.value, (size_t)size);
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else
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r = -EIO;
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mutex_unlock(&mb5_transfer.lock);
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return r;
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}
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/**
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* db5500_prcmu_abb_write() - Write register value(s) to the ABB.
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* @slave: The I2C slave address.
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* @reg: The (start) register address.
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* @value: The value(s) to write.
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* @size: The number of registers to write.
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*
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* Writes register value(s) to the ABB.
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* @size has to be <= 4.
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*/
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int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
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{
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int r;
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if ((size < 1) || (4 < size))
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return -EINVAL;
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mutex_lock(&mb5_transfer.lock);
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
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cpu_relax();
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writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
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writeb(reg, PRCM_REQ_MB5_I2C_REG);
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writeb(size, PRCM_REQ_MB5_I2C_SIZE);
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memcpy_toio(PRCM_REQ_MB5_I2C_DATA, value, size);
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writeb(MB5H_I2C_WRITE, PRCM_REQ_MB5_HEADER);
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writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
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wait_for_completion(&mb5_transfer.work);
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if ((mb5_transfer.ack.header == MB5H_I2C_WRITE) &&
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(mb5_transfer.ack.status == RC_SUCCESS))
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r = 0;
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else
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r = -EIO;
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mutex_unlock(&mb5_transfer.lock);
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return r;
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}
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int db5500_prcmu_enable_dsipll(void)
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{
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int i;
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/* Enable DSIPLL_RESETN resets */
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writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
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/* Unclamp DSIPLL in/out */
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writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
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/* Set DSI PLL FREQ */
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writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
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writel(PRCMU_DSI_PLLOUT_SEL_SETTING,
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PRCM_DSI_PLLOUT_SEL);
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/* Enable Escape clocks */
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writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
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/* Start DSI PLL */
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writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
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/* Reset DSI PLL */
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writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
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for (i = 0; i < 10; i++) {
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if ((readl(PRCM_PLLDSI_LOCKP) &
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PRCMU_PLLDSI_LOCKP_LOCKED) == PRCMU_PLLDSI_LOCKP_LOCKED)
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break;
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udelay(100);
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}
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/* Release DSIPLL_RESETN */
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writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
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return 0;
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}
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int db5500_prcmu_disable_dsipll(void)
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{
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/* Disable dsi pll */
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writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
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/* Disable escapeclock */
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writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
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return 0;
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}
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int db5500_prcmu_set_display_clocks(void)
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{
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/* HDMI and TVCLK Should be handled somewhere else */
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/* PLLDIV=8, PLLSW=2, CLKEN=1 */
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writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
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/* PLLDIV=14, PLLSW=2, CLKEN=1 */
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writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
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return 0;
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}
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static void ack_dbb_wakeup(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&mb0_transfer.lock, flags);
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while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
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cpu_relax();
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writeb(RMB0H_RD_WAKE_UP_ACK, PRCM_REQ_MB0_HEADER);
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writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
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spin_unlock_irqrestore(&mb0_transfer.lock, flags);
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}
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static inline void print_unknown_header_warning(u8 n, u8 header)
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{
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pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
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header, n);
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}
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static bool read_mailbox_0(void)
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{
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bool r;
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u8 header;
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header = readb(PRCM_ACK_MB0_HEADER);
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switch (header) {
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case AMB0H_WAKE_UP:
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r = true;
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break;
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default:
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print_unknown_header_warning(0, header);
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r = false;
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break;
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}
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writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
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return r;
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}
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static bool read_mailbox_1(void)
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{
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writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
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return false;
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}
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static bool read_mailbox_2(void)
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{
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writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
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return false;
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}
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static bool read_mailbox_3(void)
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{
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writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
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return false;
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}
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static bool read_mailbox_4(void)
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{
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writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
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return false;
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}
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static bool read_mailbox_5(void)
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{
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u8 header;
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header = readb(PRCM_ACK_MB5_HEADER);
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switch (header) {
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case MB5H_I2C_READ:
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memcpy_fromio(mb5_transfer.ack.value, PRCM_ACK_MB5_I2C_DATA, 4);
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case MB5H_I2C_WRITE:
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mb5_transfer.ack.header = header;
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mb5_transfer.ack.status = readb(PRCM_ACK_MB5_RETURN_CODE);
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complete(&mb5_transfer.work);
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break;
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default:
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print_unknown_header_warning(5, header);
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break;
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}
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writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
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return false;
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}
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static bool read_mailbox_6(void)
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{
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writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
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return false;
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}
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static bool read_mailbox_7(void)
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{
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writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
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return false;
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}
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static bool (* const read_mailbox[NUM_MB])(void) = {
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read_mailbox_0,
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read_mailbox_1,
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read_mailbox_2,
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read_mailbox_3,
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read_mailbox_4,
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read_mailbox_5,
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read_mailbox_6,
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read_mailbox_7
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};
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static irqreturn_t prcmu_irq_handler(int irq, void *data)
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{
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u32 bits;
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u8 n;
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irqreturn_t r;
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bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
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if (unlikely(!bits))
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return IRQ_NONE;
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r = IRQ_HANDLED;
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for (n = 0; bits; n++) {
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if (bits & MBOX_BIT(n)) {
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bits -= MBOX_BIT(n);
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if (read_mailbox[n]())
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r = IRQ_WAKE_THREAD;
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}
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}
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return r;
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}
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static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
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{
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ack_dbb_wakeup();
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return IRQ_HANDLED;
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}
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void __init db5500_prcmu_early_init(void)
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{
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tcdm_base = __io_address(U5500_PRCMU_TCDM_BASE);
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spin_lock_init(&mb0_transfer.lock);
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mutex_init(&mb5_transfer.lock);
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init_completion(&mb5_transfer.work);
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}
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/**
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* prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
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*
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*/
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int __init db5500_prcmu_init(void)
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{
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int r = 0;
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if (ux500_is_svp() || !cpu_is_u5500())
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return -ENODEV;
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/* Clean up the mailbox interrupts after pre-kernel code. */
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writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLEAR);
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r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler,
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prcmu_irq_thread_fn, 0, "prcmu", NULL);
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if (r < 0) {
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pr_err("prcmu: Failed to allocate IRQ_DB5500_PRCMU1.\n");
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return -EBUSY;
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}
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return 0;
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}
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arch_initcall(db5500_prcmu_init);
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