931 lines
24 KiB
C
931 lines
24 KiB
C
/*
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* Copyright (c) 2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "core.h"
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#include "hw.h"
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#include "reg.h"
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#include "phy.h"
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static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
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/* We can tune this as we go by monitoring really low values */
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#define ATH9K_NF_TOO_LOW -60
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/* AR5416 may return very high value (like -31 dBm), in those cases the nf
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* is incorrect and we should use the static NF value. Later we can try to
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* find out why they are reporting these values */
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static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
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{
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if (nf > ATH9K_NF_TOO_LOW) {
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DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
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"%s: noise floor value detected (%d) is "
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"lower than what we think is a "
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"reasonable value (%d)\n",
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__func__, nf, ATH9K_NF_TOO_LOW);
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return false;
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}
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return true;
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}
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static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
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{
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int16_t nfval;
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int16_t sort[ATH9K_NF_CAL_HIST_MAX];
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int i, j;
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for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
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sort[i] = nfCalBuffer[i];
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for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
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for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
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if (sort[j] > sort[j - 1]) {
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nfval = sort[j];
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sort[j] = sort[j - 1];
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sort[j - 1] = nfval;
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}
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}
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}
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nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
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return nfval;
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}
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static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
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int16_t *nfarray)
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{
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int i;
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for (i = 0; i < NUM_NF_READINGS; i++) {
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h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
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if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
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h[i].currIndex = 0;
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if (h[i].invalidNFcount > 0) {
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if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
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nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
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h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
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} else {
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h[i].invalidNFcount--;
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h[i].privNF = nfarray[i];
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}
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} else {
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h[i].privNF =
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ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
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}
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}
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return;
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}
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static void ath9k_hw_do_getnf(struct ath_hal *ah,
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int16_t nfarray[NUM_NF_READINGS])
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{
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int16_t nf;
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if (AR_SREV_9280_10_OR_LATER(ah))
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nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
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else
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nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"NF calibrated [ctl] [chain 0] is %d\n", nf);
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nfarray[0] = nf;
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if (AR_SREV_9280_10_OR_LATER(ah))
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nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
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AR9280_PHY_CH1_MINCCA_PWR);
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else
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nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
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AR_PHY_CH1_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
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"NF calibrated [ctl] [chain 1] is %d\n", nf);
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nfarray[1] = nf;
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if (!AR_SREV_9280(ah)) {
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nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
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AR_PHY_CH2_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
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"NF calibrated [ctl] [chain 2] is %d\n", nf);
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nfarray[2] = nf;
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}
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if (AR_SREV_9280_10_OR_LATER(ah))
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nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
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AR9280_PHY_EXT_MINCCA_PWR);
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else
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nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
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AR_PHY_EXT_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
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"NF calibrated [ext] [chain 0] is %d\n", nf);
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nfarray[3] = nf;
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if (AR_SREV_9280_10_OR_LATER(ah))
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nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
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AR9280_PHY_CH1_EXT_MINCCA_PWR);
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else
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nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
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AR_PHY_CH1_EXT_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"NF calibrated [ext] [chain 1] is %d\n", nf);
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nfarray[4] = nf;
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if (!AR_SREV_9280(ah)) {
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nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
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AR_PHY_CH2_EXT_MINCCA_PWR);
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if (nf & 0x100)
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nf = 0 - ((nf ^ 0x1ff) + 1);
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DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
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"NF calibrated [ext] [chain 2] is %d\n", nf);
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nfarray[5] = nf;
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}
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}
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static bool getNoiseFloorThresh(struct ath_hal *ah,
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const struct ath9k_channel *chan,
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int16_t *nft)
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{
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switch (chan->chanmode) {
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case CHANNEL_A:
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case CHANNEL_A_HT20:
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case CHANNEL_A_HT40PLUS:
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case CHANNEL_A_HT40MINUS:
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*nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5);
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break;
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case CHANNEL_B:
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case CHANNEL_G:
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case CHANNEL_G_HT20:
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case CHANNEL_G_HT40PLUS:
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case CHANNEL_G_HT40MINUS:
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*nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2);
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break;
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default:
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DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
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"%s: invalid channel flags 0x%x\n", __func__,
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chan->channelFlags);
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return false;
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}
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return true;
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}
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static void ath9k_hw_setup_calibration(struct ath_hal *ah,
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struct hal_cal_list *currCal)
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{
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REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
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AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
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currCal->calData->calCountMax);
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switch (currCal->calData->calType) {
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case IQ_MISMATCH_CAL:
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REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"%s: starting IQ Mismatch Calibration\n",
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__func__);
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break;
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case ADC_GAIN_CAL:
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REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"%s: starting ADC Gain Calibration\n", __func__);
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break;
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case ADC_DC_CAL:
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REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"%s: starting ADC DC Calibration\n", __func__);
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break;
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case ADC_DC_INIT_CAL:
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REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"%s: starting Init ADC DC Calibration\n",
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__func__);
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break;
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}
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REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
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AR_PHY_TIMING_CTRL4_DO_CAL);
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}
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static void ath9k_hw_reset_calibration(struct ath_hal *ah,
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struct hal_cal_list *currCal)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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int i;
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ath9k_hw_setup_calibration(ah, currCal);
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currCal->calState = CAL_RUNNING;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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ahp->ah_Meas0.sign[i] = 0;
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ahp->ah_Meas1.sign[i] = 0;
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ahp->ah_Meas2.sign[i] = 0;
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ahp->ah_Meas3.sign[i] = 0;
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}
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ahp->ah_CalSamples = 0;
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}
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static void ath9k_hw_per_calibration(struct ath_hal *ah,
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struct ath9k_channel *ichan,
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u8 rxchainmask,
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struct hal_cal_list *currCal,
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bool *isCalDone)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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*isCalDone = false;
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if (currCal->calState == CAL_RUNNING) {
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if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
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AR_PHY_TIMING_CTRL4_DO_CAL)) {
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currCal->calData->calCollect(ah);
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ahp->ah_CalSamples++;
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if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) {
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int i, numChains = 0;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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if (rxchainmask & (1 << i))
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numChains++;
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}
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currCal->calData->calPostProc(ah, numChains);
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ichan->CalValid |= currCal->calData->calType;
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currCal->calState = CAL_DONE;
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*isCalDone = true;
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} else {
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ath9k_hw_setup_calibration(ah, currCal);
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}
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}
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} else if (!(ichan->CalValid & currCal->calData->calType)) {
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ath9k_hw_reset_calibration(ah, currCal);
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}
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}
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static bool ath9k_hw_iscal_supported(struct ath_hal *ah,
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struct ath9k_channel *chan,
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enum hal_cal_types calType)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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bool retval = false;
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switch (calType & ahp->ah_suppCals) {
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case IQ_MISMATCH_CAL:
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if (!IS_CHAN_B(chan))
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retval = true;
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break;
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case ADC_GAIN_CAL:
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case ADC_DC_CAL:
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if (!IS_CHAN_B(chan)
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&& !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
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retval = true;
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break;
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}
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return retval;
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}
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static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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int i;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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ahp->ah_totalPowerMeasI[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
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ahp->ah_totalPowerMeasQ[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
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ahp->ah_totalIqCorrMeas[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
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ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
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ahp->ah_totalPowerMeasQ[i],
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ahp->ah_totalIqCorrMeas[i]);
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}
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}
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static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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int i;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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ahp->ah_totalAdcIOddPhase[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
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ahp->ah_totalAdcIEvenPhase[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
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ahp->ah_totalAdcQOddPhase[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
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ahp->ah_totalAdcQEvenPhase[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
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"oddq=0x%08x; evenq=0x%08x;\n",
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ahp->ah_CalSamples, i,
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ahp->ah_totalAdcIOddPhase[i],
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ahp->ah_totalAdcIEvenPhase[i],
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ahp->ah_totalAdcQOddPhase[i],
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ahp->ah_totalAdcQEvenPhase[i]);
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}
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}
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static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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int i;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
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ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
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ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
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ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
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"oddq=0x%08x; evenq=0x%08x;\n",
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ahp->ah_CalSamples, i,
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ahp->ah_totalAdcDcOffsetIOddPhase[i],
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ahp->ah_totalAdcDcOffsetIEvenPhase[i],
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ahp->ah_totalAdcDcOffsetQOddPhase[i],
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ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
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}
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}
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static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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u32 powerMeasQ, powerMeasI, iqCorrMeas;
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u32 qCoffDenom, iCoffDenom;
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int32_t qCoff, iCoff;
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int iqCorrNeg, i;
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for (i = 0; i < numChains; i++) {
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powerMeasI = ahp->ah_totalPowerMeasI[i];
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powerMeasQ = ahp->ah_totalPowerMeasQ[i];
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iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"Starting IQ Cal and Correction for Chain %d\n",
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i);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"Orignal: Chn %diq_corr_meas = 0x%08x\n",
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i, ahp->ah_totalIqCorrMeas[i]);
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iqCorrNeg = 0;
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if (iqCorrMeas > 0x80000000) {
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iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
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iqCorrNeg = 1;
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}
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
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iqCorrNeg);
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iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
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qCoffDenom = powerMeasQ / 64;
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if (powerMeasQ != 0) {
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iCoff = iqCorrMeas / iCoffDenom;
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qCoff = powerMeasI / qCoffDenom - 64;
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"Chn %d iCoff = 0x%08x\n", i, iCoff);
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"Chn %d qCoff = 0x%08x\n", i, qCoff);
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iCoff = iCoff & 0x3f;
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DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
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"New: Chn %d iCoff = 0x%08x\n", i, iCoff);
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if (iqCorrNeg == 0x0)
|
|
iCoff = 0x40 - iCoff;
|
|
|
|
if (qCoff > 15)
|
|
qCoff = 15;
|
|
else if (qCoff <= -16)
|
|
qCoff = 16;
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
|
|
i, iCoff, qCoff);
|
|
|
|
REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
|
|
AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
|
|
iCoff);
|
|
REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
|
|
AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
|
|
qCoff);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"IQ Cal and Correction done for Chain %d\n",
|
|
i);
|
|
}
|
|
}
|
|
|
|
REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
|
|
AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
|
|
}
|
|
|
|
static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
|
|
u32 qGainMismatch, iGainMismatch, val, i;
|
|
|
|
for (i = 0; i < numChains; i++) {
|
|
iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
|
|
iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
|
|
qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
|
|
qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Starting ADC Gain Cal for Chain %d\n", i);
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d pwr_meas_odd_i = 0x%08x\n", i,
|
|
iOddMeasOffset);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d pwr_meas_even_i = 0x%08x\n", i,
|
|
iEvenMeasOffset);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d pwr_meas_odd_q = 0x%08x\n", i,
|
|
qOddMeasOffset);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d pwr_meas_even_q = 0x%08x\n", i,
|
|
qEvenMeasOffset);
|
|
|
|
if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
|
|
iGainMismatch =
|
|
((iEvenMeasOffset * 32) /
|
|
iOddMeasOffset) & 0x3f;
|
|
qGainMismatch =
|
|
((qOddMeasOffset * 32) /
|
|
qEvenMeasOffset) & 0x3f;
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d gain_mismatch_i = 0x%08x\n", i,
|
|
iGainMismatch);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d gain_mismatch_q = 0x%08x\n", i,
|
|
qGainMismatch);
|
|
|
|
val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
|
|
val &= 0xfffff000;
|
|
val |= (qGainMismatch) | (iGainMismatch << 6);
|
|
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"ADC Gain Cal done for Chain %d\n", i);
|
|
}
|
|
}
|
|
|
|
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
|
|
REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
|
|
AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
|
|
}
|
|
|
|
static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
u32 iOddMeasOffset, iEvenMeasOffset, val, i;
|
|
int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
|
|
const struct hal_percal_data *calData =
|
|
ahp->ah_cal_list_curr->calData;
|
|
u32 numSamples =
|
|
(1 << (calData->calCountMax + 5)) * calData->calNumSamples;
|
|
|
|
for (i = 0; i < numChains; i++) {
|
|
iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
|
|
iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
|
|
qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
|
|
qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Starting ADC DC Offset Cal for Chain %d\n", i);
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d pwr_meas_odd_i = %d\n", i,
|
|
iOddMeasOffset);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d pwr_meas_even_i = %d\n", i,
|
|
iEvenMeasOffset);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d pwr_meas_odd_q = %d\n", i,
|
|
qOddMeasOffset);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d pwr_meas_even_q = %d\n", i,
|
|
qEvenMeasOffset);
|
|
|
|
iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
|
|
numSamples) & 0x1ff;
|
|
qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
|
|
numSamples) & 0x1ff;
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
|
|
iDcMismatch);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
|
|
qDcMismatch);
|
|
|
|
val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
|
|
val &= 0xc0000fff;
|
|
val |= (qDcMismatch << 12) | (iDcMismatch << 21);
|
|
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"ADC DC Offset Cal done for Chain %d\n", i);
|
|
}
|
|
|
|
REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
|
|
REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
|
|
AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
|
|
}
|
|
|
|
void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
|
|
bool *isCalDone)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
struct ath9k_channel *ichan =
|
|
ath9k_regd_check_channel(ah, chan);
|
|
struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
|
|
|
|
*isCalDone = true;
|
|
|
|
if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
|
|
return;
|
|
|
|
if (currCal == NULL)
|
|
return;
|
|
|
|
if (ichan == NULL) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"%s: invalid channel %u/0x%x; no mapping\n",
|
|
__func__, chan->channel, chan->channelFlags);
|
|
return;
|
|
}
|
|
|
|
|
|
if (currCal->calState != CAL_DONE) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"%s: Calibration state incorrect, %d\n",
|
|
__func__, currCal->calState);
|
|
return;
|
|
}
|
|
|
|
|
|
if (!ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType))
|
|
return;
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"%s: Resetting Cal %d state for channel %u/0x%x\n",
|
|
__func__, currCal->calData->calType, chan->channel,
|
|
chan->channelFlags);
|
|
|
|
ichan->CalValid &= ~currCal->calData->calType;
|
|
currCal->calState = CAL_WAITING;
|
|
|
|
*isCalDone = false;
|
|
}
|
|
|
|
void ath9k_hw_start_nfcal(struct ath_hal *ah)
|
|
{
|
|
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
|
|
AR_PHY_AGC_CONTROL_ENABLE_NF);
|
|
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
|
|
AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
|
|
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
|
|
}
|
|
|
|
void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
|
|
{
|
|
struct ath9k_nfcal_hist *h;
|
|
int i, j;
|
|
int32_t val;
|
|
const u32 ar5416_cca_regs[6] = {
|
|
AR_PHY_CCA,
|
|
AR_PHY_CH1_CCA,
|
|
AR_PHY_CH2_CCA,
|
|
AR_PHY_EXT_CCA,
|
|
AR_PHY_CH1_EXT_CCA,
|
|
AR_PHY_CH2_EXT_CCA
|
|
};
|
|
u8 chainmask;
|
|
|
|
if (AR_SREV_9280(ah))
|
|
chainmask = 0x1B;
|
|
else
|
|
chainmask = 0x3F;
|
|
|
|
#ifdef ATH_NF_PER_CHAN
|
|
h = chan->nfCalHist;
|
|
#else
|
|
h = ah->nfCalHist;
|
|
#endif
|
|
|
|
for (i = 0; i < NUM_NF_READINGS; i++) {
|
|
if (chainmask & (1 << i)) {
|
|
val = REG_READ(ah, ar5416_cca_regs[i]);
|
|
val &= 0xFFFFFE00;
|
|
val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
|
|
REG_WRITE(ah, ar5416_cca_regs[i], val);
|
|
}
|
|
}
|
|
|
|
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
|
|
AR_PHY_AGC_CONTROL_ENABLE_NF);
|
|
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
|
|
AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
|
|
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
|
|
|
|
for (j = 0; j < 1000; j++) {
|
|
if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
|
|
AR_PHY_AGC_CONTROL_NF) == 0)
|
|
break;
|
|
udelay(10);
|
|
}
|
|
|
|
for (i = 0; i < NUM_NF_READINGS; i++) {
|
|
if (chainmask & (1 << i)) {
|
|
val = REG_READ(ah, ar5416_cca_regs[i]);
|
|
val &= 0xFFFFFE00;
|
|
val |= (((u32) (-50) << 1) & 0x1ff);
|
|
REG_WRITE(ah, ar5416_cca_regs[i], val);
|
|
}
|
|
}
|
|
}
|
|
|
|
int16_t ath9k_hw_getnf(struct ath_hal *ah,
|
|
struct ath9k_channel *chan)
|
|
{
|
|
int16_t nf, nfThresh;
|
|
int16_t nfarray[NUM_NF_READINGS] = { 0 };
|
|
struct ath9k_nfcal_hist *h;
|
|
u8 chainmask;
|
|
|
|
if (AR_SREV_9280(ah))
|
|
chainmask = 0x1B;
|
|
else
|
|
chainmask = 0x3F;
|
|
|
|
chan->channelFlags &= (~CHANNEL_CW_INT);
|
|
if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"%s: NF did not complete in calibration window\n",
|
|
__func__);
|
|
nf = 0;
|
|
chan->rawNoiseFloor = nf;
|
|
return chan->rawNoiseFloor;
|
|
} else {
|
|
ath9k_hw_do_getnf(ah, nfarray);
|
|
nf = nfarray[0];
|
|
if (getNoiseFloorThresh(ah, chan, &nfThresh)
|
|
&& nf > nfThresh) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"%s: noise floor failed detected; "
|
|
"detected %d, threshold %d\n", __func__,
|
|
nf, nfThresh);
|
|
chan->channelFlags |= CHANNEL_CW_INT;
|
|
}
|
|
}
|
|
|
|
#ifdef ATH_NF_PER_CHAN
|
|
h = chan->nfCalHist;
|
|
#else
|
|
h = ah->nfCalHist;
|
|
#endif
|
|
|
|
ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
|
|
chan->rawNoiseFloor = h[0].privNF;
|
|
|
|
return chan->rawNoiseFloor;
|
|
}
|
|
|
|
void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
|
|
{
|
|
int i, j;
|
|
|
|
for (i = 0; i < NUM_NF_READINGS; i++) {
|
|
ah->nfCalHist[i].currIndex = 0;
|
|
ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
|
|
ah->nfCalHist[i].invalidNFcount =
|
|
AR_PHY_CCA_FILTERWINDOW_LENGTH;
|
|
for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
|
|
ah->nfCalHist[i].nfCalBuffer[j] =
|
|
AR_PHY_CCA_MAX_GOOD_VALUE;
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
|
|
{
|
|
struct ath9k_channel *ichan;
|
|
s16 nf;
|
|
|
|
ichan = ath9k_regd_check_channel(ah, chan);
|
|
if (ichan == NULL) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
|
|
"%s: invalid channel %u/0x%x; no mapping\n",
|
|
__func__, chan->channel, chan->channelFlags);
|
|
return ATH_DEFAULT_NOISE_FLOOR;
|
|
}
|
|
if (ichan->rawNoiseFloor == 0) {
|
|
enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
|
|
nf = NOISE_FLOOR[mode];
|
|
} else
|
|
nf = ichan->rawNoiseFloor;
|
|
|
|
if (!ath9k_hw_nf_in_range(ah, nf))
|
|
nf = ATH_DEFAULT_NOISE_FLOOR;
|
|
|
|
return nf;
|
|
}
|
|
|
|
bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
|
|
u8 rxchainmask, bool longcal,
|
|
bool *isCalDone)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
|
|
struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
|
|
|
|
*isCalDone = true;
|
|
|
|
if (ichan == NULL) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
|
|
"%s: invalid channel %u/0x%x; no mapping\n",
|
|
__func__, chan->channel, chan->channelFlags);
|
|
return false;
|
|
}
|
|
|
|
if (currCal &&
|
|
(currCal->calState == CAL_RUNNING ||
|
|
currCal->calState == CAL_WAITING)) {
|
|
ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
|
|
isCalDone);
|
|
if (*isCalDone) {
|
|
ahp->ah_cal_list_curr = currCal = currCal->calNext;
|
|
|
|
if (currCal->calState == CAL_WAITING) {
|
|
*isCalDone = false;
|
|
ath9k_hw_reset_calibration(ah, currCal);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (longcal) {
|
|
ath9k_hw_getnf(ah, ichan);
|
|
ath9k_hw_loadnf(ah, ah->ah_curchan);
|
|
ath9k_hw_start_nfcal(ah);
|
|
|
|
if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
|
|
chan->channelFlags |= CHANNEL_CW_INT;
|
|
ichan->channelFlags &= ~CHANNEL_CW_INT;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool ath9k_hw_init_cal(struct ath_hal *ah,
|
|
struct ath9k_channel *chan)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
struct ath9k_channel *ichan = ath9k_regd_check_channel(ah, chan);
|
|
|
|
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
|
|
REG_READ(ah, AR_PHY_AGC_CONTROL) |
|
|
AR_PHY_AGC_CONTROL_CAL);
|
|
|
|
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"%s: offset calibration failed to complete in 1ms; "
|
|
"noisy environment?\n", __func__);
|
|
return false;
|
|
}
|
|
|
|
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
|
|
REG_READ(ah, AR_PHY_AGC_CONTROL) |
|
|
AR_PHY_AGC_CONTROL_NF);
|
|
|
|
ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
|
|
|
|
if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
|
|
if (ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
|
|
INIT_CAL(&ahp->ah_adcGainCalData);
|
|
INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"%s: enabling ADC Gain Calibration.\n",
|
|
__func__);
|
|
}
|
|
if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
|
|
INIT_CAL(&ahp->ah_adcDcCalData);
|
|
INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"%s: enabling ADC DC Calibration.\n",
|
|
__func__);
|
|
}
|
|
if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
|
|
INIT_CAL(&ahp->ah_iqCalData);
|
|
INSERT_CAL(ahp, &ahp->ah_iqCalData);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
|
|
"%s: enabling IQ Calibration.\n",
|
|
__func__);
|
|
}
|
|
|
|
ahp->ah_cal_list_curr = ahp->ah_cal_list;
|
|
|
|
if (ahp->ah_cal_list_curr)
|
|
ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr);
|
|
}
|
|
|
|
ichan->CalValid = 0;
|
|
|
|
return true;
|
|
}
|
|
|
|
const struct hal_percal_data iq_cal_multi_sample = {
|
|
IQ_MISMATCH_CAL,
|
|
MAX_CAL_SAMPLES,
|
|
PER_MIN_LOG_COUNT,
|
|
ath9k_hw_iqcal_collect,
|
|
ath9k_hw_iqcalibrate
|
|
};
|
|
const struct hal_percal_data iq_cal_single_sample = {
|
|
IQ_MISMATCH_CAL,
|
|
MIN_CAL_SAMPLES,
|
|
PER_MAX_LOG_COUNT,
|
|
ath9k_hw_iqcal_collect,
|
|
ath9k_hw_iqcalibrate
|
|
};
|
|
const struct hal_percal_data adc_gain_cal_multi_sample = {
|
|
ADC_GAIN_CAL,
|
|
MAX_CAL_SAMPLES,
|
|
PER_MIN_LOG_COUNT,
|
|
ath9k_hw_adc_gaincal_collect,
|
|
ath9k_hw_adc_gaincal_calibrate
|
|
};
|
|
const struct hal_percal_data adc_gain_cal_single_sample = {
|
|
ADC_GAIN_CAL,
|
|
MIN_CAL_SAMPLES,
|
|
PER_MAX_LOG_COUNT,
|
|
ath9k_hw_adc_gaincal_collect,
|
|
ath9k_hw_adc_gaincal_calibrate
|
|
};
|
|
const struct hal_percal_data adc_dc_cal_multi_sample = {
|
|
ADC_DC_CAL,
|
|
MAX_CAL_SAMPLES,
|
|
PER_MIN_LOG_COUNT,
|
|
ath9k_hw_adc_dccal_collect,
|
|
ath9k_hw_adc_dccal_calibrate
|
|
};
|
|
const struct hal_percal_data adc_dc_cal_single_sample = {
|
|
ADC_DC_CAL,
|
|
MIN_CAL_SAMPLES,
|
|
PER_MAX_LOG_COUNT,
|
|
ath9k_hw_adc_dccal_collect,
|
|
ath9k_hw_adc_dccal_calibrate
|
|
};
|
|
const struct hal_percal_data adc_init_dc_cal = {
|
|
ADC_DC_INIT_CAL,
|
|
MIN_CAL_SAMPLES,
|
|
INIT_LOG_COUNT,
|
|
ath9k_hw_adc_dccal_collect,
|
|
ath9k_hw_adc_dccal_calibrate
|
|
};
|