929 lines
26 KiB
C
929 lines
26 KiB
C
/*
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* Copyright (C) 2015-2016 Marvell International Ltd.
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* This program is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation, either version 2 of the
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* License, or any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include "dmaengine.h"
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/* DMA Engine Registers */
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#define MV_XOR_V2_DMA_DESQ_BALR_OFF 0x000
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#define MV_XOR_V2_DMA_DESQ_BAHR_OFF 0x004
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#define MV_XOR_V2_DMA_DESQ_SIZE_OFF 0x008
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#define MV_XOR_V2_DMA_DESQ_DONE_OFF 0x00C
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#define MV_XOR_V2_DMA_DESQ_DONE_PENDING_MASK 0x7FFF
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#define MV_XOR_V2_DMA_DESQ_DONE_PENDING_SHIFT 0
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#define MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_MASK 0x1FFF
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#define MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_SHIFT 16
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#define MV_XOR_V2_DMA_DESQ_ARATTR_OFF 0x010
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#define MV_XOR_V2_DMA_DESQ_ATTR_CACHE_MASK 0x3F3F
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#define MV_XOR_V2_DMA_DESQ_ATTR_OUTER_SHAREABLE 0x202
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#define MV_XOR_V2_DMA_DESQ_ATTR_CACHEABLE 0x3C3C
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#define MV_XOR_V2_DMA_IMSG_CDAT_OFF 0x014
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#define MV_XOR_V2_DMA_IMSG_THRD_OFF 0x018
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#define MV_XOR_V2_DMA_IMSG_THRD_MASK 0x7FFF
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#define MV_XOR_V2_DMA_IMSG_THRD_SHIFT 0x0
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#define MV_XOR_V2_DMA_IMSG_TIMER_EN BIT(18)
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#define MV_XOR_V2_DMA_DESQ_AWATTR_OFF 0x01C
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/* Same flags as MV_XOR_V2_DMA_DESQ_ARATTR_OFF */
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#define MV_XOR_V2_DMA_DESQ_ALLOC_OFF 0x04C
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#define MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_MASK 0xFFFF
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#define MV_XOR_V2_DMA_DESQ_ALLOC_WRPTR_SHIFT 16
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#define MV_XOR_V2_DMA_IMSG_BALR_OFF 0x050
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#define MV_XOR_V2_DMA_IMSG_BAHR_OFF 0x054
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#define MV_XOR_V2_DMA_DESQ_CTRL_OFF 0x100
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#define MV_XOR_V2_DMA_DESQ_CTRL_32B 1
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#define MV_XOR_V2_DMA_DESQ_CTRL_128B 7
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#define MV_XOR_V2_DMA_DESQ_STOP_OFF 0x800
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#define MV_XOR_V2_DMA_DESQ_DEALLOC_OFF 0x804
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#define MV_XOR_V2_DMA_DESQ_ADD_OFF 0x808
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#define MV_XOR_V2_DMA_IMSG_TMOT 0x810
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#define MV_XOR_V2_DMA_IMSG_TIMER_THRD_MASK 0x1FFF
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#define MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT 0
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/* XOR Global registers */
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#define MV_XOR_V2_GLOB_BW_CTRL 0x4
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#define MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_SHIFT 0
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#define MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_VAL 64
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#define MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_SHIFT 8
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#define MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_VAL 8
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#define MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_SHIFT 12
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#define MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_VAL 4
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#define MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_SHIFT 16
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#define MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_VAL 4
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#define MV_XOR_V2_GLOB_PAUSE 0x014
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#define MV_XOR_V2_GLOB_PAUSE_AXI_TIME_DIS_VAL 0x8
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#define MV_XOR_V2_GLOB_SYS_INT_CAUSE 0x200
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#define MV_XOR_V2_GLOB_SYS_INT_MASK 0x204
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#define MV_XOR_V2_GLOB_MEM_INT_CAUSE 0x220
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#define MV_XOR_V2_GLOB_MEM_INT_MASK 0x224
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#define MV_XOR_V2_MIN_DESC_SIZE 32
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#define MV_XOR_V2_EXT_DESC_SIZE 128
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#define MV_XOR_V2_DESC_RESERVED_SIZE 12
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#define MV_XOR_V2_DESC_BUFF_D_ADDR_SIZE 12
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#define MV_XOR_V2_CMD_LINE_NUM_MAX_D_BUF 8
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/*
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* Descriptors queue size. With 32 bytes descriptors, up to 2^14
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* descriptors are allowed, with 128 bytes descriptors, up to 2^12
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* descriptors are allowed. This driver uses 128 bytes descriptors,
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* but experimentation has shown that a set of 1024 descriptors is
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* sufficient to reach a good level of performance.
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*/
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#define MV_XOR_V2_DESC_NUM 1024
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/*
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* Threshold values for descriptors and timeout, determined by
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* experimentation as giving a good level of performance.
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*/
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#define MV_XOR_V2_DONE_IMSG_THRD 0x14
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#define MV_XOR_V2_TIMER_THRD 0xB0
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/**
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* struct mv_xor_v2_descriptor - DMA HW descriptor
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* @desc_id: used by S/W and is not affected by H/W.
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* @flags: error and status flags
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* @crc32_result: CRC32 calculation result
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* @desc_ctrl: operation mode and control flags
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* @buff_size: amount of bytes to be processed
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* @fill_pattern_src_addr: Fill-Pattern or Source-Address and
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* AW-Attributes
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* @data_buff_addr: Source (and might be RAID6 destination)
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* addresses of data buffers in RAID5 and RAID6
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* @reserved: reserved
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*/
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struct mv_xor_v2_descriptor {
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u16 desc_id;
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u16 flags;
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u32 crc32_result;
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u32 desc_ctrl;
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/* Definitions for desc_ctrl */
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#define DESC_NUM_ACTIVE_D_BUF_SHIFT 22
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#define DESC_OP_MODE_SHIFT 28
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#define DESC_OP_MODE_NOP 0 /* Idle operation */
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#define DESC_OP_MODE_MEMCPY 1 /* Pure-DMA operation */
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#define DESC_OP_MODE_MEMSET 2 /* Mem-Fill operation */
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#define DESC_OP_MODE_MEMINIT 3 /* Mem-Init operation */
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#define DESC_OP_MODE_MEM_COMPARE 4 /* Mem-Compare operation */
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#define DESC_OP_MODE_CRC32 5 /* CRC32 calculation */
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#define DESC_OP_MODE_XOR 6 /* RAID5 (XOR) operation */
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#define DESC_OP_MODE_RAID6 7 /* RAID6 P&Q-generation */
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#define DESC_OP_MODE_RAID6_REC 8 /* RAID6 Recovery */
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#define DESC_Q_BUFFER_ENABLE BIT(16)
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#define DESC_P_BUFFER_ENABLE BIT(17)
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#define DESC_IOD BIT(27)
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u32 buff_size;
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u32 fill_pattern_src_addr[4];
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u32 data_buff_addr[MV_XOR_V2_DESC_BUFF_D_ADDR_SIZE];
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u32 reserved[MV_XOR_V2_DESC_RESERVED_SIZE];
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};
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/**
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* struct mv_xor_v2_device - implements a xor device
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* @lock: lock for the engine
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* @dma_base: memory mapped DMA register base
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* @glob_base: memory mapped global register base
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* @irq_tasklet:
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* @free_sw_desc: linked list of free SW descriptors
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* @dmadev: dma device
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* @dmachan: dma channel
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* @hw_desq: HW descriptors queue
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* @hw_desq_virt: virtual address of DESCQ
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* @sw_desq: SW descriptors queue
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* @desc_size: HW descriptor size
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* @npendings: number of pending descriptors (for which tx_submit has
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* been called, but not yet issue_pending)
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*/
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struct mv_xor_v2_device {
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spinlock_t lock;
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void __iomem *dma_base;
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void __iomem *glob_base;
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struct clk *clk;
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struct clk *reg_clk;
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struct tasklet_struct irq_tasklet;
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struct list_head free_sw_desc;
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struct dma_device dmadev;
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struct dma_chan dmachan;
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dma_addr_t hw_desq;
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struct mv_xor_v2_descriptor *hw_desq_virt;
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struct mv_xor_v2_sw_desc *sw_desq;
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int desc_size;
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unsigned int npendings;
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unsigned int hw_queue_idx;
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};
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/**
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* struct mv_xor_v2_sw_desc - implements a xor SW descriptor
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* @idx: descriptor index
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* @async_tx: support for the async_tx api
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* @hw_desc: assosiated HW descriptor
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* @free_list: node of the free SW descriprots list
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*/
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struct mv_xor_v2_sw_desc {
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int idx;
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struct dma_async_tx_descriptor async_tx;
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struct mv_xor_v2_descriptor hw_desc;
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struct list_head free_list;
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};
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/*
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* Fill the data buffers to a HW descriptor
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*/
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static void mv_xor_v2_set_data_buffers(struct mv_xor_v2_device *xor_dev,
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struct mv_xor_v2_descriptor *desc,
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dma_addr_t src, int index)
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{
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int arr_index = ((index >> 1) * 3);
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/*
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* Fill the buffer's addresses to the descriptor.
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*
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* The format of the buffers address for 2 sequential buffers
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* X and X + 1:
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*
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* First word: Buffer-DX-Address-Low[31:0]
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* Second word: Buffer-DX+1-Address-Low[31:0]
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* Third word: DX+1-Buffer-Address-High[47:32] [31:16]
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* DX-Buffer-Address-High[47:32] [15:0]
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*/
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if ((index & 0x1) == 0) {
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desc->data_buff_addr[arr_index] = lower_32_bits(src);
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desc->data_buff_addr[arr_index + 2] &= ~0xFFFF;
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desc->data_buff_addr[arr_index + 2] |=
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upper_32_bits(src) & 0xFFFF;
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} else {
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desc->data_buff_addr[arr_index + 1] =
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lower_32_bits(src);
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desc->data_buff_addr[arr_index + 2] &= ~0xFFFF0000;
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desc->data_buff_addr[arr_index + 2] |=
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(upper_32_bits(src) & 0xFFFF) << 16;
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}
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}
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/*
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* notify the engine of new descriptors, and update the available index.
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*/
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static void mv_xor_v2_add_desc_to_desq(struct mv_xor_v2_device *xor_dev,
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int num_of_desc)
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{
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/* write the number of new descriptors in the DESQ. */
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writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ADD_OFF);
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}
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/*
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* free HW descriptors
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*/
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static void mv_xor_v2_free_desc_from_desq(struct mv_xor_v2_device *xor_dev,
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int num_of_desc)
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{
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/* write the number of new descriptors in the DESQ. */
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writel(num_of_desc, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DEALLOC_OFF);
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}
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/*
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* Set descriptor size
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* Return the HW descriptor size in bytes
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*/
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static int mv_xor_v2_set_desc_size(struct mv_xor_v2_device *xor_dev)
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{
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writel(MV_XOR_V2_DMA_DESQ_CTRL_128B,
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xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_CTRL_OFF);
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return MV_XOR_V2_EXT_DESC_SIZE;
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}
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/*
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* Set the IMSG threshold
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*/
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static inline
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void mv_xor_v2_enable_imsg_thrd(struct mv_xor_v2_device *xor_dev)
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{
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u32 reg;
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/* Configure threshold of number of descriptors, and enable timer */
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reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF);
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reg &= (~MV_XOR_V2_DMA_IMSG_THRD_MASK << MV_XOR_V2_DMA_IMSG_THRD_SHIFT);
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reg |= (MV_XOR_V2_DONE_IMSG_THRD << MV_XOR_V2_DMA_IMSG_THRD_SHIFT);
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reg |= MV_XOR_V2_DMA_IMSG_TIMER_EN;
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writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_THRD_OFF);
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/* Configure Timer Threshold */
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reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT);
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reg &= (~MV_XOR_V2_DMA_IMSG_TIMER_THRD_MASK <<
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MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT);
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reg |= (MV_XOR_V2_TIMER_THRD << MV_XOR_V2_DMA_IMSG_TIMER_THRD_SHIFT);
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writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_TMOT);
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}
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static irqreturn_t mv_xor_v2_interrupt_handler(int irq, void *data)
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{
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struct mv_xor_v2_device *xor_dev = data;
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unsigned int ndescs;
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u32 reg;
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reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF);
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ndescs = ((reg >> MV_XOR_V2_DMA_DESQ_DONE_PENDING_SHIFT) &
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MV_XOR_V2_DMA_DESQ_DONE_PENDING_MASK);
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/* No descriptors to process */
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if (!ndescs)
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return IRQ_NONE;
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/* schedule a tasklet to handle descriptors callbacks */
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tasklet_schedule(&xor_dev->irq_tasklet);
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return IRQ_HANDLED;
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}
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/*
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* submit a descriptor to the DMA engine
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*/
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static dma_cookie_t
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mv_xor_v2_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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void *dest_hw_desc;
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dma_cookie_t cookie;
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struct mv_xor_v2_sw_desc *sw_desc =
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container_of(tx, struct mv_xor_v2_sw_desc, async_tx);
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struct mv_xor_v2_device *xor_dev =
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container_of(tx->chan, struct mv_xor_v2_device, dmachan);
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dev_dbg(xor_dev->dmadev.dev,
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"%s sw_desc %p: async_tx %p\n",
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__func__, sw_desc, &sw_desc->async_tx);
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/* assign coookie */
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spin_lock_bh(&xor_dev->lock);
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cookie = dma_cookie_assign(tx);
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/* copy the HW descriptor from the SW descriptor to the DESQ */
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dest_hw_desc = xor_dev->hw_desq_virt + xor_dev->hw_queue_idx;
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memcpy(dest_hw_desc, &sw_desc->hw_desc, xor_dev->desc_size);
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xor_dev->npendings++;
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xor_dev->hw_queue_idx++;
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if (xor_dev->hw_queue_idx >= MV_XOR_V2_DESC_NUM)
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xor_dev->hw_queue_idx = 0;
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spin_unlock_bh(&xor_dev->lock);
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return cookie;
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}
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/*
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* Prepare a SW descriptor
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*/
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static struct mv_xor_v2_sw_desc *
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mv_xor_v2_prep_sw_desc(struct mv_xor_v2_device *xor_dev)
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{
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struct mv_xor_v2_sw_desc *sw_desc;
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bool found = false;
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/* Lock the channel */
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spin_lock_bh(&xor_dev->lock);
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if (list_empty(&xor_dev->free_sw_desc)) {
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spin_unlock_bh(&xor_dev->lock);
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/* schedule tasklet to free some descriptors */
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tasklet_schedule(&xor_dev->irq_tasklet);
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return NULL;
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}
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list_for_each_entry(sw_desc, &xor_dev->free_sw_desc, free_list) {
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if (async_tx_test_ack(&sw_desc->async_tx)) {
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found = true;
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break;
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}
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}
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if (!found) {
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spin_unlock_bh(&xor_dev->lock);
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return NULL;
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}
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list_del(&sw_desc->free_list);
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/* Release the channel */
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spin_unlock_bh(&xor_dev->lock);
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return sw_desc;
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}
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/*
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* Prepare a HW descriptor for a memcpy operation
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*/
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static struct dma_async_tx_descriptor *
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mv_xor_v2_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,
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dma_addr_t src, size_t len, unsigned long flags)
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{
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struct mv_xor_v2_sw_desc *sw_desc;
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struct mv_xor_v2_descriptor *hw_descriptor;
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struct mv_xor_v2_device *xor_dev;
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xor_dev = container_of(chan, struct mv_xor_v2_device, dmachan);
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dev_dbg(xor_dev->dmadev.dev,
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"%s len: %zu src %pad dest %pad flags: %ld\n",
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__func__, len, &src, &dest, flags);
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sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
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if (!sw_desc)
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return NULL;
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sw_desc->async_tx.flags = flags;
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/* set the HW descriptor */
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hw_descriptor = &sw_desc->hw_desc;
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/* save the SW descriptor ID to restore when operation is done */
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hw_descriptor->desc_id = sw_desc->idx;
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/* Set the MEMCPY control word */
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hw_descriptor->desc_ctrl =
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DESC_OP_MODE_MEMCPY << DESC_OP_MODE_SHIFT;
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if (flags & DMA_PREP_INTERRUPT)
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hw_descriptor->desc_ctrl |= DESC_IOD;
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/* Set source address */
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hw_descriptor->fill_pattern_src_addr[0] = lower_32_bits(src);
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hw_descriptor->fill_pattern_src_addr[1] =
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upper_32_bits(src) & 0xFFFF;
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/* Set Destination address */
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hw_descriptor->fill_pattern_src_addr[2] = lower_32_bits(dest);
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hw_descriptor->fill_pattern_src_addr[3] =
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upper_32_bits(dest) & 0xFFFF;
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/* Set buffers size */
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hw_descriptor->buff_size = len;
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/* return the async tx descriptor */
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return &sw_desc->async_tx;
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}
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/*
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* Prepare a HW descriptor for a XOR operation
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*/
|
|
static struct dma_async_tx_descriptor *
|
|
mv_xor_v2_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
|
|
unsigned int src_cnt, size_t len, unsigned long flags)
|
|
{
|
|
struct mv_xor_v2_sw_desc *sw_desc;
|
|
struct mv_xor_v2_descriptor *hw_descriptor;
|
|
struct mv_xor_v2_device *xor_dev =
|
|
container_of(chan, struct mv_xor_v2_device, dmachan);
|
|
int i;
|
|
|
|
if (src_cnt > MV_XOR_V2_CMD_LINE_NUM_MAX_D_BUF || src_cnt < 1)
|
|
return NULL;
|
|
|
|
dev_dbg(xor_dev->dmadev.dev,
|
|
"%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
|
|
__func__, src_cnt, len, &dest, flags);
|
|
|
|
sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
|
|
if (!sw_desc)
|
|
return NULL;
|
|
|
|
sw_desc->async_tx.flags = flags;
|
|
|
|
/* set the HW descriptor */
|
|
hw_descriptor = &sw_desc->hw_desc;
|
|
|
|
/* save the SW descriptor ID to restore when operation is done */
|
|
hw_descriptor->desc_id = sw_desc->idx;
|
|
|
|
/* Set the XOR control word */
|
|
hw_descriptor->desc_ctrl =
|
|
DESC_OP_MODE_XOR << DESC_OP_MODE_SHIFT;
|
|
hw_descriptor->desc_ctrl |= DESC_P_BUFFER_ENABLE;
|
|
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
hw_descriptor->desc_ctrl |= DESC_IOD;
|
|
|
|
/* Set the data buffers */
|
|
for (i = 0; i < src_cnt; i++)
|
|
mv_xor_v2_set_data_buffers(xor_dev, hw_descriptor, src[i], i);
|
|
|
|
hw_descriptor->desc_ctrl |=
|
|
src_cnt << DESC_NUM_ACTIVE_D_BUF_SHIFT;
|
|
|
|
/* Set Destination address */
|
|
hw_descriptor->fill_pattern_src_addr[2] = lower_32_bits(dest);
|
|
hw_descriptor->fill_pattern_src_addr[3] =
|
|
upper_32_bits(dest) & 0xFFFF;
|
|
|
|
/* Set buffers size */
|
|
hw_descriptor->buff_size = len;
|
|
|
|
/* return the async tx descriptor */
|
|
return &sw_desc->async_tx;
|
|
}
|
|
|
|
/*
|
|
* Prepare a HW descriptor for interrupt operation.
|
|
*/
|
|
static struct dma_async_tx_descriptor *
|
|
mv_xor_v2_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
|
|
{
|
|
struct mv_xor_v2_sw_desc *sw_desc;
|
|
struct mv_xor_v2_descriptor *hw_descriptor;
|
|
struct mv_xor_v2_device *xor_dev =
|
|
container_of(chan, struct mv_xor_v2_device, dmachan);
|
|
|
|
sw_desc = mv_xor_v2_prep_sw_desc(xor_dev);
|
|
if (!sw_desc)
|
|
return NULL;
|
|
|
|
/* set the HW descriptor */
|
|
hw_descriptor = &sw_desc->hw_desc;
|
|
|
|
/* save the SW descriptor ID to restore when operation is done */
|
|
hw_descriptor->desc_id = sw_desc->idx;
|
|
|
|
/* Set the INTERRUPT control word */
|
|
hw_descriptor->desc_ctrl =
|
|
DESC_OP_MODE_NOP << DESC_OP_MODE_SHIFT;
|
|
hw_descriptor->desc_ctrl |= DESC_IOD;
|
|
|
|
/* return the async tx descriptor */
|
|
return &sw_desc->async_tx;
|
|
}
|
|
|
|
/*
|
|
* push pending transactions to hardware
|
|
*/
|
|
static void mv_xor_v2_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct mv_xor_v2_device *xor_dev =
|
|
container_of(chan, struct mv_xor_v2_device, dmachan);
|
|
|
|
spin_lock_bh(&xor_dev->lock);
|
|
|
|
/*
|
|
* update the engine with the number of descriptors to
|
|
* process
|
|
*/
|
|
mv_xor_v2_add_desc_to_desq(xor_dev, xor_dev->npendings);
|
|
xor_dev->npendings = 0;
|
|
|
|
spin_unlock_bh(&xor_dev->lock);
|
|
}
|
|
|
|
static inline
|
|
int mv_xor_v2_get_pending_params(struct mv_xor_v2_device *xor_dev,
|
|
int *pending_ptr)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_DONE_OFF);
|
|
|
|
/* get the next pending descriptor index */
|
|
*pending_ptr = ((reg >> MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_SHIFT) &
|
|
MV_XOR_V2_DMA_DESQ_DONE_READ_PTR_MASK);
|
|
|
|
/* get the number of descriptors pending handle */
|
|
return ((reg >> MV_XOR_V2_DMA_DESQ_DONE_PENDING_SHIFT) &
|
|
MV_XOR_V2_DMA_DESQ_DONE_PENDING_MASK);
|
|
}
|
|
|
|
/*
|
|
* handle the descriptors after HW process
|
|
*/
|
|
static void mv_xor_v2_tasklet(unsigned long data)
|
|
{
|
|
struct mv_xor_v2_device *xor_dev = (struct mv_xor_v2_device *) data;
|
|
int pending_ptr, num_of_pending, i;
|
|
struct mv_xor_v2_sw_desc *next_pending_sw_desc = NULL;
|
|
|
|
dev_dbg(xor_dev->dmadev.dev, "%s %d\n", __func__, __LINE__);
|
|
|
|
/* get the pending descriptors parameters */
|
|
num_of_pending = mv_xor_v2_get_pending_params(xor_dev, &pending_ptr);
|
|
|
|
/* loop over free descriptors */
|
|
for (i = 0; i < num_of_pending; i++) {
|
|
struct mv_xor_v2_descriptor *next_pending_hw_desc =
|
|
xor_dev->hw_desq_virt + pending_ptr;
|
|
|
|
/* get the SW descriptor related to the HW descriptor */
|
|
next_pending_sw_desc =
|
|
&xor_dev->sw_desq[next_pending_hw_desc->desc_id];
|
|
|
|
/* call the callback */
|
|
if (next_pending_sw_desc->async_tx.cookie > 0) {
|
|
/*
|
|
* update the channel's completed cookie - no
|
|
* lock is required the IMSG threshold provide
|
|
* the locking
|
|
*/
|
|
dma_cookie_complete(&next_pending_sw_desc->async_tx);
|
|
|
|
if (next_pending_sw_desc->async_tx.callback)
|
|
next_pending_sw_desc->async_tx.callback(
|
|
next_pending_sw_desc->async_tx.callback_param);
|
|
|
|
dma_descriptor_unmap(&next_pending_sw_desc->async_tx);
|
|
}
|
|
|
|
dma_run_dependencies(&next_pending_sw_desc->async_tx);
|
|
|
|
/* Lock the channel */
|
|
spin_lock_bh(&xor_dev->lock);
|
|
|
|
/* add the SW descriptor to the free descriptors list */
|
|
list_add(&next_pending_sw_desc->free_list,
|
|
&xor_dev->free_sw_desc);
|
|
|
|
/* Release the channel */
|
|
spin_unlock_bh(&xor_dev->lock);
|
|
|
|
/* increment the next descriptor */
|
|
pending_ptr++;
|
|
if (pending_ptr >= MV_XOR_V2_DESC_NUM)
|
|
pending_ptr = 0;
|
|
}
|
|
|
|
if (num_of_pending != 0) {
|
|
/* free the descriptores */
|
|
mv_xor_v2_free_desc_from_desq(xor_dev, num_of_pending);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Set DMA Interrupt-message (IMSG) parameters
|
|
*/
|
|
static void mv_xor_v2_set_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
|
|
{
|
|
struct mv_xor_v2_device *xor_dev = dev_get_drvdata(desc->dev);
|
|
|
|
writel(msg->address_lo,
|
|
xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_BALR_OFF);
|
|
writel(msg->address_hi & 0xFFFF,
|
|
xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_BAHR_OFF);
|
|
writel(msg->data,
|
|
xor_dev->dma_base + MV_XOR_V2_DMA_IMSG_CDAT_OFF);
|
|
}
|
|
|
|
static int mv_xor_v2_descq_init(struct mv_xor_v2_device *xor_dev)
|
|
{
|
|
u32 reg;
|
|
|
|
/* write the DESQ size to the DMA engine */
|
|
writel(MV_XOR_V2_DESC_NUM,
|
|
xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_SIZE_OFF);
|
|
|
|
/* write the DESQ address to the DMA enngine*/
|
|
writel(xor_dev->hw_desq & 0xFFFFFFFF,
|
|
xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_BALR_OFF);
|
|
writel((xor_dev->hw_desq & 0xFFFF00000000) >> 32,
|
|
xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_BAHR_OFF);
|
|
|
|
/*
|
|
* This is a temporary solution, until we activate the
|
|
* SMMU. Set the attributes for reading & writing data buffers
|
|
* & descriptors to:
|
|
*
|
|
* - OuterShareable - Snoops will be performed on CPU caches
|
|
* - Enable cacheable - Bufferable, Modifiable, Other Allocate
|
|
* and Allocate
|
|
*/
|
|
reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ARATTR_OFF);
|
|
reg &= ~MV_XOR_V2_DMA_DESQ_ATTR_CACHE_MASK;
|
|
reg |= MV_XOR_V2_DMA_DESQ_ATTR_OUTER_SHAREABLE |
|
|
MV_XOR_V2_DMA_DESQ_ATTR_CACHEABLE;
|
|
writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_ARATTR_OFF);
|
|
|
|
reg = readl(xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_AWATTR_OFF);
|
|
reg &= ~MV_XOR_V2_DMA_DESQ_ATTR_CACHE_MASK;
|
|
reg |= MV_XOR_V2_DMA_DESQ_ATTR_OUTER_SHAREABLE |
|
|
MV_XOR_V2_DMA_DESQ_ATTR_CACHEABLE;
|
|
writel(reg, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_AWATTR_OFF);
|
|
|
|
/* BW CTRL - set values to optimize the XOR performance:
|
|
*
|
|
* - Set WrBurstLen & RdBurstLen - the unit will issue
|
|
* maximum of 256B write/read transactions.
|
|
* - Limit the number of outstanding write & read data
|
|
* (OBB/IBB) requests to the maximal value.
|
|
*/
|
|
reg = ((MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_VAL <<
|
|
MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_RD_SHIFT) |
|
|
(MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_VAL <<
|
|
MV_XOR_V2_GLOB_BW_CTRL_NUM_OSTD_WR_SHIFT) |
|
|
(MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_VAL <<
|
|
MV_XOR_V2_GLOB_BW_CTRL_RD_BURST_LEN_SHIFT) |
|
|
(MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_VAL <<
|
|
MV_XOR_V2_GLOB_BW_CTRL_WR_BURST_LEN_SHIFT));
|
|
writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_BW_CTRL);
|
|
|
|
/* Disable the AXI timer feature */
|
|
reg = readl(xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE);
|
|
reg |= MV_XOR_V2_GLOB_PAUSE_AXI_TIME_DIS_VAL;
|
|
writel(reg, xor_dev->glob_base + MV_XOR_V2_GLOB_PAUSE);
|
|
|
|
/* enable the DMA engine */
|
|
writel(0, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mv_xor_v2_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
struct mv_xor_v2_device *xor_dev = platform_get_drvdata(dev);
|
|
|
|
/* Set this bit to disable to stop the XOR unit. */
|
|
writel(0x1, xor_dev->dma_base + MV_XOR_V2_DMA_DESQ_STOP_OFF);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mv_xor_v2_resume(struct platform_device *dev)
|
|
{
|
|
struct mv_xor_v2_device *xor_dev = platform_get_drvdata(dev);
|
|
|
|
mv_xor_v2_set_desc_size(xor_dev);
|
|
mv_xor_v2_enable_imsg_thrd(xor_dev);
|
|
mv_xor_v2_descq_init(xor_dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mv_xor_v2_probe(struct platform_device *pdev)
|
|
{
|
|
struct mv_xor_v2_device *xor_dev;
|
|
struct resource *res;
|
|
int i, ret = 0;
|
|
struct dma_device *dma_dev;
|
|
struct mv_xor_v2_sw_desc *sw_desc;
|
|
struct msi_desc *msi_desc;
|
|
|
|
BUILD_BUG_ON(sizeof(struct mv_xor_v2_descriptor) !=
|
|
MV_XOR_V2_EXT_DESC_SIZE);
|
|
|
|
xor_dev = devm_kzalloc(&pdev->dev, sizeof(*xor_dev), GFP_KERNEL);
|
|
if (!xor_dev)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
xor_dev->dma_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(xor_dev->dma_base))
|
|
return PTR_ERR(xor_dev->dma_base);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
xor_dev->glob_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(xor_dev->glob_base))
|
|
return PTR_ERR(xor_dev->glob_base);
|
|
|
|
platform_set_drvdata(pdev, xor_dev);
|
|
|
|
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
|
|
if (ret)
|
|
return ret;
|
|
|
|
xor_dev->reg_clk = devm_clk_get(&pdev->dev, "reg");
|
|
if (PTR_ERR(xor_dev->reg_clk) != -ENOENT) {
|
|
if (!IS_ERR(xor_dev->reg_clk)) {
|
|
ret = clk_prepare_enable(xor_dev->reg_clk);
|
|
if (ret)
|
|
return ret;
|
|
} else {
|
|
return PTR_ERR(xor_dev->reg_clk);
|
|
}
|
|
}
|
|
|
|
xor_dev->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(xor_dev->clk) && PTR_ERR(xor_dev->clk) == -EPROBE_DEFER) {
|
|
ret = EPROBE_DEFER;
|
|
goto disable_reg_clk;
|
|
}
|
|
if (!IS_ERR(xor_dev->clk)) {
|
|
ret = clk_prepare_enable(xor_dev->clk);
|
|
if (ret)
|
|
goto disable_reg_clk;
|
|
}
|
|
|
|
ret = platform_msi_domain_alloc_irqs(&pdev->dev, 1,
|
|
mv_xor_v2_set_msi_msg);
|
|
if (ret)
|
|
goto disable_clk;
|
|
|
|
msi_desc = first_msi_entry(&pdev->dev);
|
|
if (!msi_desc)
|
|
goto free_msi_irqs;
|
|
|
|
ret = devm_request_irq(&pdev->dev, msi_desc->irq,
|
|
mv_xor_v2_interrupt_handler, 0,
|
|
dev_name(&pdev->dev), xor_dev);
|
|
if (ret)
|
|
goto free_msi_irqs;
|
|
|
|
tasklet_init(&xor_dev->irq_tasklet, mv_xor_v2_tasklet,
|
|
(unsigned long) xor_dev);
|
|
|
|
xor_dev->desc_size = mv_xor_v2_set_desc_size(xor_dev);
|
|
|
|
dma_cookie_init(&xor_dev->dmachan);
|
|
|
|
/*
|
|
* allocate coherent memory for hardware descriptors
|
|
* note: writecombine gives slightly better performance, but
|
|
* requires that we explicitly flush the writes
|
|
*/
|
|
xor_dev->hw_desq_virt =
|
|
dma_alloc_coherent(&pdev->dev,
|
|
xor_dev->desc_size * MV_XOR_V2_DESC_NUM,
|
|
&xor_dev->hw_desq, GFP_KERNEL);
|
|
if (!xor_dev->hw_desq_virt) {
|
|
ret = -ENOMEM;
|
|
goto free_msi_irqs;
|
|
}
|
|
|
|
/* alloc memory for the SW descriptors */
|
|
xor_dev->sw_desq = devm_kzalloc(&pdev->dev, sizeof(*sw_desc) *
|
|
MV_XOR_V2_DESC_NUM, GFP_KERNEL);
|
|
if (!xor_dev->sw_desq) {
|
|
ret = -ENOMEM;
|
|
goto free_hw_desq;
|
|
}
|
|
|
|
spin_lock_init(&xor_dev->lock);
|
|
|
|
/* init the free SW descriptors list */
|
|
INIT_LIST_HEAD(&xor_dev->free_sw_desc);
|
|
|
|
/* add all SW descriptors to the free list */
|
|
for (i = 0; i < MV_XOR_V2_DESC_NUM; i++) {
|
|
struct mv_xor_v2_sw_desc *sw_desc =
|
|
xor_dev->sw_desq + i;
|
|
sw_desc->idx = i;
|
|
dma_async_tx_descriptor_init(&sw_desc->async_tx,
|
|
&xor_dev->dmachan);
|
|
sw_desc->async_tx.tx_submit = mv_xor_v2_tx_submit;
|
|
async_tx_ack(&sw_desc->async_tx);
|
|
|
|
list_add(&sw_desc->free_list,
|
|
&xor_dev->free_sw_desc);
|
|
}
|
|
|
|
dma_dev = &xor_dev->dmadev;
|
|
|
|
/* set DMA capabilities */
|
|
dma_cap_zero(dma_dev->cap_mask);
|
|
dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
|
|
dma_cap_set(DMA_XOR, dma_dev->cap_mask);
|
|
dma_cap_set(DMA_INTERRUPT, dma_dev->cap_mask);
|
|
|
|
/* init dma link list */
|
|
INIT_LIST_HEAD(&dma_dev->channels);
|
|
|
|
/* set base routines */
|
|
dma_dev->device_tx_status = dma_cookie_status;
|
|
dma_dev->device_issue_pending = mv_xor_v2_issue_pending;
|
|
dma_dev->dev = &pdev->dev;
|
|
|
|
dma_dev->device_prep_dma_memcpy = mv_xor_v2_prep_dma_memcpy;
|
|
dma_dev->device_prep_dma_interrupt = mv_xor_v2_prep_dma_interrupt;
|
|
dma_dev->max_xor = 8;
|
|
dma_dev->device_prep_dma_xor = mv_xor_v2_prep_dma_xor;
|
|
|
|
xor_dev->dmachan.device = dma_dev;
|
|
|
|
list_add_tail(&xor_dev->dmachan.device_node,
|
|
&dma_dev->channels);
|
|
|
|
mv_xor_v2_enable_imsg_thrd(xor_dev);
|
|
|
|
mv_xor_v2_descq_init(xor_dev);
|
|
|
|
ret = dma_async_device_register(dma_dev);
|
|
if (ret)
|
|
goto free_hw_desq;
|
|
|
|
dev_notice(&pdev->dev, "Marvell Version 2 XOR driver\n");
|
|
|
|
return 0;
|
|
|
|
free_hw_desq:
|
|
dma_free_coherent(&pdev->dev,
|
|
xor_dev->desc_size * MV_XOR_V2_DESC_NUM,
|
|
xor_dev->hw_desq_virt, xor_dev->hw_desq);
|
|
free_msi_irqs:
|
|
platform_msi_domain_free_irqs(&pdev->dev);
|
|
disable_clk:
|
|
clk_disable_unprepare(xor_dev->clk);
|
|
disable_reg_clk:
|
|
clk_disable_unprepare(xor_dev->reg_clk);
|
|
return ret;
|
|
}
|
|
|
|
static int mv_xor_v2_remove(struct platform_device *pdev)
|
|
{
|
|
struct mv_xor_v2_device *xor_dev = platform_get_drvdata(pdev);
|
|
|
|
dma_async_device_unregister(&xor_dev->dmadev);
|
|
|
|
dma_free_coherent(&pdev->dev,
|
|
xor_dev->desc_size * MV_XOR_V2_DESC_NUM,
|
|
xor_dev->hw_desq_virt, xor_dev->hw_desq);
|
|
|
|
platform_msi_domain_free_irqs(&pdev->dev);
|
|
|
|
clk_disable_unprepare(xor_dev->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id mv_xor_v2_dt_ids[] = {
|
|
{ .compatible = "marvell,xor-v2", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mv_xor_v2_dt_ids);
|
|
#endif
|
|
|
|
static struct platform_driver mv_xor_v2_driver = {
|
|
.probe = mv_xor_v2_probe,
|
|
.suspend = mv_xor_v2_suspend,
|
|
.resume = mv_xor_v2_resume,
|
|
.remove = mv_xor_v2_remove,
|
|
.driver = {
|
|
.name = "mv_xor_v2",
|
|
.of_match_table = of_match_ptr(mv_xor_v2_dt_ids),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mv_xor_v2_driver);
|
|
|
|
MODULE_DESCRIPTION("DMA engine driver for Marvell's Version 2 of XOR engine");
|
|
MODULE_LICENSE("GPL");
|