798 lines
22 KiB
C
798 lines
22 KiB
C
// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
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/*******************************************************************************
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*
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* Module Name: hwregs - Read/write access functions for the various ACPI
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* control and status registers.
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*
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******************************************************************************/
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#include <acpi/acpi.h>
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#include "accommon.h"
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#include "acevents.h"
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#define _COMPONENT ACPI_HARDWARE
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ACPI_MODULE_NAME("hwregs")
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#if (!ACPI_REDUCED_HARDWARE)
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/* Local Prototypes */
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static u8
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acpi_hw_get_access_bit_width(u64 address,
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struct acpi_generic_address *reg,
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u8 max_bit_width);
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static acpi_status
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acpi_hw_read_multiple(u32 *value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b);
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static acpi_status
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acpi_hw_write_multiple(u32 value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b);
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#endif /* !ACPI_REDUCED_HARDWARE */
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_get_access_bit_width
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*
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* PARAMETERS: address - GAS register address
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* reg - GAS register structure
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* max_bit_width - Max bit_width supported (32 or 64)
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*
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* RETURN: Status
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*
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* DESCRIPTION: Obtain optimal access bit width
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*
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******************************************************************************/
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static u8
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acpi_hw_get_access_bit_width(u64 address,
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struct acpi_generic_address *reg, u8 max_bit_width)
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{
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u8 access_bit_width;
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/*
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* GAS format "register", used by FADT:
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* 1. Detected if bit_offset is 0 and bit_width is 8/16/32/64;
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* 2. access_size field is ignored and bit_width field is used for
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* determining the boundary of the IO accesses.
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* GAS format "region", used by APEI registers:
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* 1. Detected if bit_offset is not 0 or bit_width is not 8/16/32/64;
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* 2. access_size field is used for determining the boundary of the
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* IO accesses;
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* 3. bit_offset/bit_width fields are used to describe the "region".
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*
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* Note: This algorithm assumes that the "Address" fields should always
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* contain aligned values.
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*/
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if (!reg->bit_offset && reg->bit_width &&
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ACPI_IS_POWER_OF_TWO(reg->bit_width) &&
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ACPI_IS_ALIGNED(reg->bit_width, 8)) {
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access_bit_width = reg->bit_width;
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} else if (reg->access_width) {
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access_bit_width = ACPI_ACCESS_BIT_WIDTH(reg->access_width);
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} else {
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access_bit_width =
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ACPI_ROUND_UP_POWER_OF_TWO_8(reg->bit_offset +
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reg->bit_width);
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if (access_bit_width <= 8) {
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access_bit_width = 8;
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} else {
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while (!ACPI_IS_ALIGNED(address, access_bit_width >> 3)) {
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access_bit_width >>= 1;
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}
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}
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}
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/* Maximum IO port access bit width is 32 */
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if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
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max_bit_width = 32;
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}
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/*
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* Return access width according to the requested maximum access bit width,
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* as the caller should know the format of the register and may enforce
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* a 32-bit accesses.
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*/
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if (access_bit_width < max_bit_width) {
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return (access_bit_width);
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}
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return (max_bit_width);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_validate_register
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*
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* PARAMETERS: reg - GAS register structure
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* max_bit_width - Max bit_width supported (32 or 64)
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* address - Pointer to where the gas->address
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* is returned
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*
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* RETURN: Status
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*
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* DESCRIPTION: Validate the contents of a GAS register. Checks the GAS
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* pointer, Address, space_id, bit_width, and bit_offset.
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*
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******************************************************************************/
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acpi_status
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acpi_hw_validate_register(struct acpi_generic_address *reg,
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u8 max_bit_width, u64 *address)
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{
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u8 bit_width;
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u8 access_width;
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/* Must have a valid pointer to a GAS structure */
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if (!reg) {
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return (AE_BAD_PARAMETER);
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}
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/*
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* Copy the target address. This handles possible alignment issues.
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* Address must not be null. A null address also indicates an optional
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* ACPI register that is not supported, so no error message.
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*/
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ACPI_MOVE_64_TO_64(address, ®->address);
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if (!(*address)) {
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return (AE_BAD_ADDRESS);
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}
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/* Validate the space_ID */
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if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) &&
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(reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) {
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ACPI_ERROR((AE_INFO,
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"Unsupported address space: 0x%X", reg->space_id));
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return (AE_SUPPORT);
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}
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/* Validate the access_width */
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if (reg->access_width > 4) {
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ACPI_ERROR((AE_INFO,
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"Unsupported register access width: 0x%X",
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reg->access_width));
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return (AE_SUPPORT);
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}
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/* Validate the bit_width, convert access_width into number of bits */
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access_width =
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acpi_hw_get_access_bit_width(*address, reg, max_bit_width);
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bit_width =
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ACPI_ROUND_UP(reg->bit_offset + reg->bit_width, access_width);
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if (max_bit_width < bit_width) {
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ACPI_WARNING((AE_INFO,
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"Requested bit width 0x%X is smaller than register bit width 0x%X",
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max_bit_width, bit_width));
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return (AE_SUPPORT);
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}
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return (AE_OK);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_read
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*
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* PARAMETERS: value - Where the value is returned
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* reg - GAS register structure
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*
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* RETURN: Status
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*
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* DESCRIPTION: Read from either memory or IO space. This is a 64-bit max
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* version of acpi_read.
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*
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* LIMITATIONS: <These limitations also apply to acpi_hw_write>
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* space_ID must be system_memory or system_IO.
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*
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******************************************************************************/
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acpi_status acpi_hw_read(u64 *value, struct acpi_generic_address *reg)
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{
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u64 address;
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u8 access_width;
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u32 bit_width;
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u8 bit_offset;
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u64 value64;
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u32 value32;
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u8 index;
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acpi_status status;
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ACPI_FUNCTION_NAME(hw_read);
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/* Validate contents of the GAS register */
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status = acpi_hw_validate_register(reg, 64, &address);
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if (ACPI_FAILURE(status)) {
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return (status);
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}
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/*
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* Initialize entire 64-bit return value to zero, convert access_width
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* into number of bits based
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*/
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*value = 0;
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access_width = acpi_hw_get_access_bit_width(address, reg, 64);
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bit_width = reg->bit_offset + reg->bit_width;
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bit_offset = reg->bit_offset;
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/*
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* Two address spaces supported: Memory or IO. PCI_Config is
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* not supported here because the GAS structure is insufficient
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*/
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index = 0;
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while (bit_width) {
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if (bit_offset >= access_width) {
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value64 = 0;
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bit_offset -= access_width;
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} else {
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if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
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status =
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acpi_os_read_memory((acpi_physical_address)
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address +
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index *
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ACPI_DIV_8
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(access_width),
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&value64, access_width);
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} else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
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status = acpi_hw_read_port((acpi_io_address)
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address +
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index *
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ACPI_DIV_8
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(access_width),
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&value32,
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access_width);
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value64 = (u64)value32;
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}
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}
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/*
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* Use offset style bit writes because "Index * AccessWidth" is
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* ensured to be less than 64-bits by acpi_hw_validate_register().
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*/
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ACPI_SET_BITS(value, index * access_width,
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ACPI_MASK_BITS_ABOVE_64(access_width), value64);
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bit_width -=
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bit_width > access_width ? access_width : bit_width;
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index++;
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}
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ACPI_DEBUG_PRINT((ACPI_DB_IO,
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"Read: %8.8X%8.8X width %2d from %8.8X%8.8X (%s)\n",
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ACPI_FORMAT_UINT64(*value), access_width,
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ACPI_FORMAT_UINT64(address),
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acpi_ut_get_region_name(reg->space_id)));
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return (status);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_write
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*
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* PARAMETERS: value - Value to be written
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* reg - GAS register structure
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*
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* RETURN: Status
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*
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* DESCRIPTION: Write to either memory or IO space. This is a 64-bit max
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* version of acpi_write.
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*
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******************************************************************************/
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acpi_status acpi_hw_write(u64 value, struct acpi_generic_address *reg)
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{
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u64 address;
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u8 access_width;
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u32 bit_width;
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u8 bit_offset;
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u64 value64;
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u8 index;
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acpi_status status;
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ACPI_FUNCTION_NAME(hw_write);
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/* Validate contents of the GAS register */
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status = acpi_hw_validate_register(reg, 64, &address);
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if (ACPI_FAILURE(status)) {
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return (status);
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}
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/* Convert access_width into number of bits based */
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access_width = acpi_hw_get_access_bit_width(address, reg, 64);
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bit_width = reg->bit_offset + reg->bit_width;
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bit_offset = reg->bit_offset;
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/*
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* Two address spaces supported: Memory or IO. PCI_Config is
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* not supported here because the GAS structure is insufficient
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*/
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index = 0;
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while (bit_width) {
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/*
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* Use offset style bit reads because "Index * AccessWidth" is
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* ensured to be less than 64-bits by acpi_hw_validate_register().
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*/
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value64 = ACPI_GET_BITS(&value, index * access_width,
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ACPI_MASK_BITS_ABOVE_64(access_width));
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if (bit_offset >= access_width) {
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bit_offset -= access_width;
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} else {
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if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
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status =
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acpi_os_write_memory((acpi_physical_address)
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address +
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index *
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ACPI_DIV_8
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(access_width),
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value64, access_width);
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} else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */
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status = acpi_hw_write_port((acpi_io_address)
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address +
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index *
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ACPI_DIV_8
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(access_width),
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(u32)value64,
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access_width);
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}
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}
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/*
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* Index * access_width is ensured to be less than 32-bits by
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* acpi_hw_validate_register().
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*/
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bit_width -=
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bit_width > access_width ? access_width : bit_width;
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index++;
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}
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ACPI_DEBUG_PRINT((ACPI_DB_IO,
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"Wrote: %8.8X%8.8X width %2d to %8.8X%8.8X (%s)\n",
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ACPI_FORMAT_UINT64(value), access_width,
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ACPI_FORMAT_UINT64(address),
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acpi_ut_get_region_name(reg->space_id)));
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return (status);
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}
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#if (!ACPI_REDUCED_HARDWARE)
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/*******************************************************************************
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*
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* FUNCTION: acpi_hw_clear_acpi_status
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*
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* PARAMETERS: None
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*
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* RETURN: Status
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*
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* DESCRIPTION: Clears all fixed and general purpose status bits
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*
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******************************************************************************/
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acpi_status acpi_hw_clear_acpi_status(void)
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{
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acpi_status status;
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acpi_cpu_flags lock_flags = 0;
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ACPI_FUNCTION_TRACE(hw_clear_acpi_status);
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ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
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ACPI_BITMASK_ALL_FIXED_STATUS,
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ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status.address)));
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lock_flags = acpi_os_acquire_raw_lock(acpi_gbl_hardware_lock);
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/* Clear the fixed events in PM1 A/B */
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status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS,
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ACPI_BITMASK_ALL_FIXED_STATUS);
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acpi_os_release_raw_lock(acpi_gbl_hardware_lock, lock_flags);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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/* Clear the GPE Bits in all GPE registers in all GPE blocks */
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status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL);
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exit:
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return_ACPI_STATUS(status);
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}
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/*******************************************************************************
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*
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* FUNCTION: acpi_hw_get_bit_register_info
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*
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* PARAMETERS: register_id - Index of ACPI Register to access
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*
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* RETURN: The bitmask to be used when accessing the register
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*
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* DESCRIPTION: Map register_id into a register bitmask.
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*
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******************************************************************************/
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struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
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{
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ACPI_FUNCTION_ENTRY();
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if (register_id > ACPI_BITREG_MAX) {
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ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: 0x%X",
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register_id));
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return (NULL);
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}
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return (&acpi_gbl_bit_register_info[register_id]);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_write_pm1_control
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*
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* PARAMETERS: pm1a_control - Value to be written to PM1A control
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* pm1b_control - Value to be written to PM1B control
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*
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* RETURN: Status
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*
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* DESCRIPTION: Write the PM1 A/B control registers. These registers are
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* different than than the PM1 A/B status and enable registers
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* in that different values can be written to the A/B registers.
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* Most notably, the SLP_TYP bits can be different, as per the
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* values returned from the _Sx predefined methods.
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*
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******************************************************************************/
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acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control)
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{
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acpi_status status;
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ACPI_FUNCTION_TRACE(hw_write_pm1_control);
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status =
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acpi_hw_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block);
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if (ACPI_FAILURE(status)) {
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return_ACPI_STATUS(status);
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}
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if (acpi_gbl_FADT.xpm1b_control_block.address) {
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status =
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acpi_hw_write(pm1b_control,
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&acpi_gbl_FADT.xpm1b_control_block);
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}
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return_ACPI_STATUS(status);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_register_read
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*
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* PARAMETERS: register_id - ACPI Register ID
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* return_value - Where the register value is returned
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*
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* RETURN: Status and the value read.
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*
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* DESCRIPTION: Read from the specified ACPI register
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*
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******************************************************************************/
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acpi_status acpi_hw_register_read(u32 register_id, u32 *return_value)
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{
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u32 value = 0;
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u64 value64;
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acpi_status status;
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ACPI_FUNCTION_TRACE(hw_register_read);
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switch (register_id) {
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case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
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status = acpi_hw_read_multiple(&value,
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&acpi_gbl_xpm1a_status,
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&acpi_gbl_xpm1b_status);
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break;
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case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
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status = acpi_hw_read_multiple(&value,
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&acpi_gbl_xpm1a_enable,
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&acpi_gbl_xpm1b_enable);
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break;
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case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
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status = acpi_hw_read_multiple(&value,
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&acpi_gbl_FADT.
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xpm1a_control_block,
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&acpi_gbl_FADT.
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xpm1b_control_block);
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/*
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* Zero the write-only bits. From the ACPI specification, "Hardware
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* Write-Only Bits": "Upon reads to registers with write-only bits,
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* software masks out all write-only bits."
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*/
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value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
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break;
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case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
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status =
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acpi_hw_read(&value64, &acpi_gbl_FADT.xpm2_control_block);
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value = (u32)value64;
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break;
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case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
|
|
|
|
status = acpi_hw_read(&value64, &acpi_gbl_FADT.xpm_timer_block);
|
|
value = (u32)value64;
|
|
break;
|
|
|
|
case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
|
|
|
|
status =
|
|
acpi_hw_read_port(acpi_gbl_FADT.smi_command, &value, 8);
|
|
break;
|
|
|
|
default:
|
|
|
|
ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
|
|
status = AE_BAD_PARAMETER;
|
|
break;
|
|
}
|
|
|
|
if (ACPI_SUCCESS(status)) {
|
|
*return_value = (u32)value;
|
|
}
|
|
|
|
return_ACPI_STATUS(status);
|
|
}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: acpi_hw_register_write
|
|
*
|
|
* PARAMETERS: register_id - ACPI Register ID
|
|
* value - The value to write
|
|
*
|
|
* RETURN: Status
|
|
*
|
|
* DESCRIPTION: Write to the specified ACPI register
|
|
*
|
|
* NOTE: In accordance with the ACPI specification, this function automatically
|
|
* preserves the value of the following bits, meaning that these bits cannot be
|
|
* changed via this interface:
|
|
*
|
|
* PM1_CONTROL[0] = SCI_EN
|
|
* PM1_CONTROL[9]
|
|
* PM1_STATUS[11]
|
|
*
|
|
* ACPI References:
|
|
* 1) Hardware Ignored Bits: When software writes to a register with ignored
|
|
* bit fields, it preserves the ignored bit fields
|
|
* 2) SCI_EN: OSPM always preserves this bit position
|
|
*
|
|
******************************************************************************/
|
|
|
|
acpi_status acpi_hw_register_write(u32 register_id, u32 value)
|
|
{
|
|
acpi_status status;
|
|
u32 read_value;
|
|
u64 read_value64;
|
|
|
|
ACPI_FUNCTION_TRACE(hw_register_write);
|
|
|
|
switch (register_id) {
|
|
case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
|
|
/*
|
|
* Handle the "ignored" bit in PM1 Status. According to the ACPI
|
|
* specification, ignored bits are to be preserved when writing.
|
|
* Normally, this would mean a read/modify/write sequence. However,
|
|
* preserving a bit in the status register is different. Writing a
|
|
* one clears the status, and writing a zero preserves the status.
|
|
* Therefore, we must always write zero to the ignored bit.
|
|
*
|
|
* This behavior is clarified in the ACPI 4.0 specification.
|
|
*/
|
|
value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
|
|
|
|
status = acpi_hw_write_multiple(value,
|
|
&acpi_gbl_xpm1a_status,
|
|
&acpi_gbl_xpm1b_status);
|
|
break;
|
|
|
|
case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
|
|
|
|
status = acpi_hw_write_multiple(value,
|
|
&acpi_gbl_xpm1a_enable,
|
|
&acpi_gbl_xpm1b_enable);
|
|
break;
|
|
|
|
case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
|
|
/*
|
|
* Perform a read first to preserve certain bits (per ACPI spec)
|
|
* Note: This includes SCI_EN, we never want to change this bit
|
|
*/
|
|
status = acpi_hw_read_multiple(&read_value,
|
|
&acpi_gbl_FADT.
|
|
xpm1a_control_block,
|
|
&acpi_gbl_FADT.
|
|
xpm1b_control_block);
|
|
if (ACPI_FAILURE(status)) {
|
|
goto exit;
|
|
}
|
|
|
|
/* Insert the bits to be preserved */
|
|
|
|
ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS,
|
|
read_value);
|
|
|
|
/* Now we can write the data */
|
|
|
|
status = acpi_hw_write_multiple(value,
|
|
&acpi_gbl_FADT.
|
|
xpm1a_control_block,
|
|
&acpi_gbl_FADT.
|
|
xpm1b_control_block);
|
|
break;
|
|
|
|
case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
|
|
/*
|
|
* For control registers, all reserved bits must be preserved,
|
|
* as per the ACPI spec.
|
|
*/
|
|
status =
|
|
acpi_hw_read(&read_value64,
|
|
&acpi_gbl_FADT.xpm2_control_block);
|
|
if (ACPI_FAILURE(status)) {
|
|
goto exit;
|
|
}
|
|
read_value = (u32)read_value64;
|
|
|
|
/* Insert the bits to be preserved */
|
|
|
|
ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS,
|
|
read_value);
|
|
|
|
status =
|
|
acpi_hw_write(value, &acpi_gbl_FADT.xpm2_control_block);
|
|
break;
|
|
|
|
case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
|
|
|
|
status = acpi_hw_write(value, &acpi_gbl_FADT.xpm_timer_block);
|
|
break;
|
|
|
|
case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
|
|
|
|
/* SMI_CMD is currently always in IO space */
|
|
|
|
status =
|
|
acpi_hw_write_port(acpi_gbl_FADT.smi_command, value, 8);
|
|
break;
|
|
|
|
default:
|
|
|
|
ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id));
|
|
status = AE_BAD_PARAMETER;
|
|
break;
|
|
}
|
|
|
|
exit:
|
|
return_ACPI_STATUS(status);
|
|
}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: acpi_hw_read_multiple
|
|
*
|
|
* PARAMETERS: value - Where the register value is returned
|
|
* register_a - First ACPI register (required)
|
|
* register_b - Second ACPI register (optional)
|
|
*
|
|
* RETURN: Status
|
|
*
|
|
* DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
|
|
*
|
|
******************************************************************************/
|
|
|
|
static acpi_status
|
|
acpi_hw_read_multiple(u32 *value,
|
|
struct acpi_generic_address *register_a,
|
|
struct acpi_generic_address *register_b)
|
|
{
|
|
u32 value_a = 0;
|
|
u32 value_b = 0;
|
|
u64 value64;
|
|
acpi_status status;
|
|
|
|
/* The first register is always required */
|
|
|
|
status = acpi_hw_read(&value64, register_a);
|
|
if (ACPI_FAILURE(status)) {
|
|
return (status);
|
|
}
|
|
value_a = (u32)value64;
|
|
|
|
/* Second register is optional */
|
|
|
|
if (register_b->address) {
|
|
status = acpi_hw_read(&value64, register_b);
|
|
if (ACPI_FAILURE(status)) {
|
|
return (status);
|
|
}
|
|
value_b = (u32)value64;
|
|
}
|
|
|
|
/*
|
|
* OR the two return values together. No shifting or masking is necessary,
|
|
* because of how the PM1 registers are defined in the ACPI specification:
|
|
*
|
|
* "Although the bits can be split between the two register blocks (each
|
|
* register block has a unique pointer within the FADT), the bit positions
|
|
* are maintained. The register block with unimplemented bits (that is,
|
|
* those implemented in the other register block) always returns zeros,
|
|
* and writes have no side effects"
|
|
*/
|
|
*value = (value_a | value_b);
|
|
return (AE_OK);
|
|
}
|
|
|
|
/******************************************************************************
|
|
*
|
|
* FUNCTION: acpi_hw_write_multiple
|
|
*
|
|
* PARAMETERS: value - The value to write
|
|
* register_a - First ACPI register (required)
|
|
* register_b - Second ACPI register (optional)
|
|
*
|
|
* RETURN: Status
|
|
*
|
|
* DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
|
|
*
|
|
******************************************************************************/
|
|
|
|
static acpi_status
|
|
acpi_hw_write_multiple(u32 value,
|
|
struct acpi_generic_address *register_a,
|
|
struct acpi_generic_address *register_b)
|
|
{
|
|
acpi_status status;
|
|
|
|
/* The first register is always required */
|
|
|
|
status = acpi_hw_write(value, register_a);
|
|
if (ACPI_FAILURE(status)) {
|
|
return (status);
|
|
}
|
|
|
|
/*
|
|
* Second register is optional
|
|
*
|
|
* No bit shifting or clearing is necessary, because of how the PM1
|
|
* registers are defined in the ACPI specification:
|
|
*
|
|
* "Although the bits can be split between the two register blocks (each
|
|
* register block has a unique pointer within the FADT), the bit positions
|
|
* are maintained. The register block with unimplemented bits (that is,
|
|
* those implemented in the other register block) always returns zeros,
|
|
* and writes have no side effects"
|
|
*/
|
|
if (register_b->address) {
|
|
status = acpi_hw_write(value, register_b);
|
|
}
|
|
|
|
return (status);
|
|
}
|
|
|
|
#endif /* !ACPI_REDUCED_HARDWARE */
|