300 lines
9.0 KiB
C
300 lines
9.0 KiB
C
/*
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* linux/arch/arm/mach-omap2/pm-domain.c
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*
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* Power domain functions for OMAP2
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*
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* Copyright (C) 2006 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*
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* Some code based on earlier OMAP2 sample PM code
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#include "prcm-regs.h"
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/* Power domain offsets */
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#define PM_MPU_OFFSET 0x100
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#define PM_CORE_OFFSET 0x200
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#define PM_GFX_OFFSET 0x300
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#define PM_WKUP_OFFSET 0x400 /* Autoidle only */
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#define PM_PLL_OFFSET 0x500 /* Autoidle only */
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#define PM_DSP_OFFSET 0x800
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#define PM_MDM_OFFSET 0xc00
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/* Power domain wake-up dependency control register */
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#define PM_WKDEP_OFFSET 0xc8
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#define EN_MDM (1 << 5)
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#define EN_WKUP (1 << 4)
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#define EN_GFX (1 << 3)
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#define EN_DSP (1 << 2)
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#define EN_MPU (1 << 1)
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#define EN_CORE (1 << 0)
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/* Core power domain state transition control register */
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#define PM_PWSTCTRL_OFFSET 0xe0
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#define FORCESTATE (1 << 18) /* Only for DSP & GFX */
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#define MEM4RETSTATE (1 << 6)
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#define MEM3RETSTATE (1 << 5)
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#define MEM2RETSTATE (1 << 4)
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#define MEM1RETSTATE (1 << 3)
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#define LOGICRETSTATE (1 << 2) /* Logic is retained */
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#define POWERSTATE_OFF 0x3
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#define POWERSTATE_RETENTION 0x1
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#define POWERSTATE_ON 0x0
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/* Power domain state register */
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#define PM_PWSTST_OFFSET 0xe4
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/* Hardware supervised state transition control register */
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#define CM_CLKSTCTRL_OFFSET 0x48
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#define AUTOSTAT_MPU (1 << 0) /* MPU */
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#define AUTOSTAT_DSS (1 << 2) /* Core */
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#define AUTOSTAT_L4 (1 << 1) /* Core */
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#define AUTOSTAT_L3 (1 << 0) /* Core */
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#define AUTOSTAT_GFX (1 << 0) /* GFX */
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#define AUTOSTAT_IVA (1 << 8) /* 2420 IVA in DSP domain */
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#define AUTOSTAT_DSP (1 << 0) /* DSP */
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#define AUTOSTAT_MDM (1 << 0) /* MDM */
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/* Automatic control of interface clock idling */
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#define CM_AUTOIDLE1_OFFSET 0x30
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#define CM_AUTOIDLE2_OFFSET 0x34 /* Core only */
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#define CM_AUTOIDLE3_OFFSET 0x38 /* Core only */
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#define CM_AUTOIDLE4_OFFSET 0x3c /* Core only */
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#define AUTO_54M(x) (((x) & 0x3) << 6)
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#define AUTO_96M(x) (((x) & 0x3) << 2)
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#define AUTO_DPLL(x) (((x) & 0x3) << 0)
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#define AUTO_STOPPED 0x3
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#define AUTO_BYPASS_FAST 0x2 /* DPLL only */
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#define AUTO_BYPASS_LOW_POWER 0x1 /* DPLL only */
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#define AUTO_DISABLED 0x0
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/* Voltage control PRCM_VOLTCTRL bits */
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#define AUTO_EXTVOLT (1 << 15)
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#define FORCE_EXTVOLT (1 << 14)
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#define SETOFF_LEVEL(x) (((x) & 0x3) << 12)
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#define MEMRETCTRL (1 << 8)
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#define SETRET_LEVEL(x) (((x) & 0x3) << 6)
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#define VOLT_LEVEL(x) (((x) & 0x3) << 0)
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#define OMAP24XX_PRCM_VBASE IO_ADDRESS(OMAP24XX_PRCM_BASE)
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#define prcm_readl(r) __raw_readl(OMAP24XX_PRCM_VBASE + (r))
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#define prcm_writel(v, r) __raw_writel((v), OMAP24XX_PRCM_VBASE + (r))
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static u32 pmdomain_get_wakeup_dependencies(int domain_offset)
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{
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return prcm_readl(domain_offset + PM_WKDEP_OFFSET);
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}
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static void pmdomain_set_wakeup_dependencies(u32 state, int domain_offset)
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{
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prcm_writel(state, domain_offset + PM_WKDEP_OFFSET);
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}
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static u32 pmdomain_get_powerstate(int domain_offset)
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{
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return prcm_readl(domain_offset + PM_PWSTCTRL_OFFSET);
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}
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static void pmdomain_set_powerstate(u32 state, int domain_offset)
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{
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prcm_writel(state, domain_offset + PM_PWSTCTRL_OFFSET);
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}
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static u32 pmdomain_get_clock_autocontrol(int domain_offset)
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{
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return prcm_readl(domain_offset + CM_CLKSTCTRL_OFFSET);
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}
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static void pmdomain_set_clock_autocontrol(u32 state, int domain_offset)
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{
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prcm_writel(state, domain_offset + CM_CLKSTCTRL_OFFSET);
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}
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static u32 pmdomain_get_clock_autoidle1(int domain_offset)
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{
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return prcm_readl(domain_offset + CM_AUTOIDLE1_OFFSET);
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}
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/* Core domain only */
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static u32 pmdomain_get_clock_autoidle2(int domain_offset)
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{
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return prcm_readl(domain_offset + CM_AUTOIDLE2_OFFSET);
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}
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/* Core domain only */
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static u32 pmdomain_get_clock_autoidle3(int domain_offset)
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{
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return prcm_readl(domain_offset + CM_AUTOIDLE3_OFFSET);
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}
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/* Core domain only */
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static u32 pmdomain_get_clock_autoidle4(int domain_offset)
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{
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return prcm_readl(domain_offset + CM_AUTOIDLE4_OFFSET);
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}
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static void pmdomain_set_clock_autoidle1(u32 state, int domain_offset)
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{
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prcm_writel(state, CM_AUTOIDLE1_OFFSET + domain_offset);
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}
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/* Core domain only */
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static void pmdomain_set_clock_autoidle2(u32 state, int domain_offset)
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{
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prcm_writel(state, CM_AUTOIDLE2_OFFSET + domain_offset);
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}
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/* Core domain only */
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static void pmdomain_set_clock_autoidle3(u32 state, int domain_offset)
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{
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prcm_writel(state, CM_AUTOIDLE3_OFFSET + domain_offset);
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}
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/* Core domain only */
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static void pmdomain_set_clock_autoidle4(u32 state, int domain_offset)
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{
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prcm_writel(state, CM_AUTOIDLE4_OFFSET + domain_offset);
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}
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/*
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* Configures power management domains to idle clocks automatically.
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*/
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void pmdomain_set_autoidle(void)
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{
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u32 val;
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/* Set PLL auto stop for 54M, 96M & DPLL */
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pmdomain_set_clock_autoidle1(AUTO_54M(AUTO_STOPPED) |
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AUTO_96M(AUTO_STOPPED) |
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AUTO_DPLL(AUTO_STOPPED), PM_PLL_OFFSET);
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/* External clock input control
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* REVISIT: Should this be in clock framework?
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*/
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PRCM_CLKSRC_CTRL |= (0x3 << 3);
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/* Configure number of 32KHz clock cycles for sys_clk */
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PRCM_CLKSSETUP = 0x00ff;
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/* Configure automatic voltage transition */
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PRCM_VOLTSETUP = 0;
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val = PRCM_VOLTCTRL;
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val &= ~(SETOFF_LEVEL(0x3) | VOLT_LEVEL(0x3));
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val |= SETOFF_LEVEL(1) | VOLT_LEVEL(1) | AUTO_EXTVOLT;
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PRCM_VOLTCTRL = val;
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/* Disable emulation tools functional clock */
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PRCM_CLKEMUL_CTRL = 0x0;
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/* Set core memory retention state */
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val = pmdomain_get_powerstate(PM_CORE_OFFSET);
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if (cpu_is_omap2420()) {
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val &= ~(0x7 << 3);
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val |= (MEM3RETSTATE | MEM2RETSTATE | MEM1RETSTATE);
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} else {
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val &= ~(0xf << 3);
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val |= (MEM4RETSTATE | MEM3RETSTATE | MEM2RETSTATE |
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MEM1RETSTATE);
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}
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pmdomain_set_powerstate(val, PM_CORE_OFFSET);
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/* OCP interface smart idle. REVISIT: Enable autoidle bit0 ? */
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val = SMS_SYSCONFIG;
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val &= ~(0x3 << 3);
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val |= (0x2 << 3) | (1 << 0);
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SMS_SYSCONFIG |= val;
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val = SDRC_SYSCONFIG;
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val &= ~(0x3 << 3);
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val |= (0x2 << 3);
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SDRC_SYSCONFIG = val;
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/* Configure L3 interface for smart idle.
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* REVISIT: Enable autoidle bit0 ?
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*/
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val = GPMC_SYSCONFIG;
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val &= ~(0x3 << 3);
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val |= (0x2 << 3) | (1 << 0);
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GPMC_SYSCONFIG = val;
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pmdomain_set_powerstate(LOGICRETSTATE | POWERSTATE_RETENTION,
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PM_MPU_OFFSET);
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pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_CORE_OFFSET);
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if (!cpu_is_omap2420())
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pmdomain_set_powerstate(POWERSTATE_RETENTION, PM_MDM_OFFSET);
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/* Assume suspend function has saved the state for DSP and GFX */
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pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_DSP_OFFSET);
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pmdomain_set_powerstate(FORCESTATE | POWERSTATE_OFF, PM_GFX_OFFSET);
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#if 0
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/* REVISIT: Internal USB needs special handling */
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force_standby_usb();
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if (cpu_is_omap2430())
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force_hsmmc();
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sdram_self_refresh_on_idle_req(1);
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#endif
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/* Enable clock auto control for all domains.
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* Note that CORE domain includes also DSS, L4 & L3.
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*/
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pmdomain_set_clock_autocontrol(AUTOSTAT_MPU, PM_MPU_OFFSET);
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pmdomain_set_clock_autocontrol(AUTOSTAT_GFX, PM_GFX_OFFSET);
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pmdomain_set_clock_autocontrol(AUTOSTAT_DSS | AUTOSTAT_L4 | AUTOSTAT_L3,
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PM_CORE_OFFSET);
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if (cpu_is_omap2420())
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pmdomain_set_clock_autocontrol(AUTOSTAT_IVA | AUTOSTAT_DSP,
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PM_DSP_OFFSET);
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else {
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pmdomain_set_clock_autocontrol(AUTOSTAT_DSP, PM_DSP_OFFSET);
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pmdomain_set_clock_autocontrol(AUTOSTAT_MDM, PM_MDM_OFFSET);
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}
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/* Enable clock autoidle for all domains */
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pmdomain_set_clock_autoidle1(0x2, PM_DSP_OFFSET);
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if (cpu_is_omap2420()) {
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pmdomain_set_clock_autoidle1(0xfffffff9, PM_CORE_OFFSET);
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pmdomain_set_clock_autoidle2(0x7, PM_CORE_OFFSET);
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pmdomain_set_clock_autoidle1(0x3f, PM_WKUP_OFFSET);
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} else {
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pmdomain_set_clock_autoidle1(0xeafffff1, PM_CORE_OFFSET);
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pmdomain_set_clock_autoidle2(0xfff, PM_CORE_OFFSET);
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pmdomain_set_clock_autoidle1(0x7f, PM_WKUP_OFFSET);
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pmdomain_set_clock_autoidle1(0x3, PM_MDM_OFFSET);
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}
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pmdomain_set_clock_autoidle3(0x7, PM_CORE_OFFSET);
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pmdomain_set_clock_autoidle4(0x1f, PM_CORE_OFFSET);
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}
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/*
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* Initializes power domains by removing wake-up dependencies and powering
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* down DSP and GFX. Gets called from PM init. Note that DSP and IVA code
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* must re-enable DSP and GFX when used.
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*/
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void __init pmdomain_init(void)
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{
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/* Remove all domain wakeup dependencies */
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pmdomain_set_wakeup_dependencies(EN_WKUP | EN_CORE, PM_MPU_OFFSET);
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pmdomain_set_wakeup_dependencies(0, PM_DSP_OFFSET);
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pmdomain_set_wakeup_dependencies(0, PM_GFX_OFFSET);
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pmdomain_set_wakeup_dependencies(EN_WKUP | EN_MPU, PM_CORE_OFFSET);
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if (cpu_is_omap2430())
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pmdomain_set_wakeup_dependencies(0, PM_MDM_OFFSET);
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/* Power down DSP and GFX */
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pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_DSP_OFFSET);
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pmdomain_set_powerstate(POWERSTATE_OFF | FORCESTATE, PM_GFX_OFFSET);
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}
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