411 lines
10 KiB
C
411 lines
10 KiB
C
#ifndef _ASM_IA64_BITOPS_H
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#define _ASM_IA64_BITOPS_H
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/*
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* Copyright (C) 1998-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*
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* 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64 O(1)
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* scheduler patch
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*/
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/bitops.h>
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#include <asm/intrinsics.h>
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*
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* The address must be (at least) "long" aligned.
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* Note that there are driver (e.g., eepro100) which use these operations to operate on
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* hw-defined data-structures, so we can't easily change these operations to force a
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* bigger alignment.
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*
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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static __inline__ void
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set_bit (int nr, volatile void *addr)
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{
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__u32 bit, old, new;
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volatile __u32 *m;
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CMPXCHG_BUGCHECK_DECL
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m = (volatile __u32 *) addr + (nr >> 5);
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bit = 1 << (nr & 31);
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do {
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CMPXCHG_BUGCHECK(m);
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old = *m;
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new = old | bit;
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} while (cmpxchg_acq(m, old, new) != old);
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}
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/**
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* __set_bit - Set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike set_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __inline__ void
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__set_bit (int nr, volatile void *addr)
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{
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*((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
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}
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/*
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* clear_bit() has "acquire" semantics.
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*/
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() do { /* skip */; } while (0)
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static __inline__ void
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clear_bit (int nr, volatile void *addr)
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{
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__u32 mask, old, new;
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volatile __u32 *m;
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CMPXCHG_BUGCHECK_DECL
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m = (volatile __u32 *) addr + (nr >> 5);
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mask = ~(1 << (nr & 31));
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do {
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CMPXCHG_BUGCHECK(m);
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old = *m;
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new = old & mask;
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} while (cmpxchg_acq(m, old, new) != old);
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}
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/**
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* __clear_bit - Clears a bit in memory (non-atomic version)
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*/
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static __inline__ void
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__clear_bit (int nr, volatile void *addr)
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{
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volatile __u32 *p = (__u32 *) addr + (nr >> 5);
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__u32 m = 1 << (nr & 31);
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*p &= ~m;
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void
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change_bit (int nr, volatile void *addr)
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{
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__u32 bit, old, new;
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volatile __u32 *m;
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CMPXCHG_BUGCHECK_DECL
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m = (volatile __u32 *) addr + (nr >> 5);
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bit = (1 << (nr & 31));
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do {
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CMPXCHG_BUGCHECK(m);
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old = *m;
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new = old ^ bit;
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} while (cmpxchg_acq(m, old, new) != old);
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}
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/**
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __inline__ void
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__change_bit (int nr, volatile void *addr)
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{
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*((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int
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test_and_set_bit (int nr, volatile void *addr)
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{
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__u32 bit, old, new;
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volatile __u32 *m;
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CMPXCHG_BUGCHECK_DECL
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m = (volatile __u32 *) addr + (nr >> 5);
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bit = 1 << (nr & 31);
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do {
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CMPXCHG_BUGCHECK(m);
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old = *m;
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new = old | bit;
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} while (cmpxchg_acq(m, old, new) != old);
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return (old & bit) != 0;
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}
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/**
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* __test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static __inline__ int
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__test_and_set_bit (int nr, volatile void *addr)
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{
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__u32 *p = (__u32 *) addr + (nr >> 5);
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__u32 m = 1 << (nr & 31);
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int oldbitset = (*p & m) != 0;
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*p |= m;
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return oldbitset;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int
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test_and_clear_bit (int nr, volatile void *addr)
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{
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__u32 mask, old, new;
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volatile __u32 *m;
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CMPXCHG_BUGCHECK_DECL
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m = (volatile __u32 *) addr + (nr >> 5);
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mask = ~(1 << (nr & 31));
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do {
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CMPXCHG_BUGCHECK(m);
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old = *m;
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new = old & mask;
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} while (cmpxchg_acq(m, old, new) != old);
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return (old & ~mask) != 0;
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}
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/**
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* __test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static __inline__ int
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__test_and_clear_bit(int nr, volatile void * addr)
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{
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__u32 *p = (__u32 *) addr + (nr >> 5);
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__u32 m = 1 << (nr & 31);
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int oldbitset = *p & m;
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*p &= ~m;
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return oldbitset;
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int
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test_and_change_bit (int nr, volatile void *addr)
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{
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__u32 bit, old, new;
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volatile __u32 *m;
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CMPXCHG_BUGCHECK_DECL
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m = (volatile __u32 *) addr + (nr >> 5);
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bit = (1 << (nr & 31));
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do {
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CMPXCHG_BUGCHECK(m);
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old = *m;
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new = old ^ bit;
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} while (cmpxchg_acq(m, old, new) != old);
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return (old & bit) != 0;
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}
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/*
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* WARNING: non atomic version.
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*/
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static __inline__ int
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__test_and_change_bit (int nr, void *addr)
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{
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__u32 old, bit = (1 << (nr & 31));
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__u32 *m = (__u32 *) addr + (nr >> 5);
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old = *m;
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*m = old ^ bit;
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return (old & bit) != 0;
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}
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static __inline__ int
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test_bit (int nr, const volatile void *addr)
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{
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return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
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}
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/**
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* ffz - find the first zero bit in a long word
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* @x: The long word to find the bit in
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*
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* Returns the bit-number (0..63) of the first (least significant) zero bit. Undefined if
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* no zero exists, so code should check against ~0UL first...
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*/
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static inline unsigned long
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ffz (unsigned long x)
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{
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unsigned long result;
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result = ia64_popcnt(x & (~x - 1));
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return result;
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}
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/**
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* __ffs - find first bit in word.
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* @x: The word to search
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*
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* Undefined if no bit exists, so code should check against 0 first.
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*/
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static __inline__ unsigned long
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__ffs (unsigned long x)
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{
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unsigned long result;
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result = ia64_popcnt((x-1) & ~x);
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return result;
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}
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#ifdef __KERNEL__
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/*
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* find_last_zero_bit - find the last zero bit in a 64 bit quantity
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* @x: The value to search
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*/
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static inline unsigned long
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ia64_fls (unsigned long x)
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{
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long double d = x;
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long exp;
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exp = ia64_getf_exp(d);
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return exp - 0xffff;
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}
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static inline int
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fls (int x)
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{
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return ia64_fls((unsigned int) x);
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}
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/*
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* ffs: find first bit set. This is defined the same way as the libc and compiler builtin
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* ffs routines, therefore differs in spirit from the above ffz (man ffs): it operates on
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* "int" values only and the result value is the bit number + 1. ffs(0) is defined to
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* return zero.
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*/
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#define ffs(x) __builtin_ffs(x)
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/*
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* hweightN: returns the hamming weight (i.e. the number
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* of bits set) of a N-bit word
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*/
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static __inline__ unsigned long
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hweight64 (unsigned long x)
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{
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unsigned long result;
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result = ia64_popcnt(x);
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return result;
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}
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#define hweight32(x) (unsigned int) hweight64((x) & 0xfffffffful)
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#define hweight16(x) (unsigned int) hweight64((x) & 0xfffful)
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#define hweight8(x) (unsigned int) hweight64((x) & 0xfful)
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#endif /* __KERNEL__ */
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extern int __find_next_zero_bit (const void *addr, unsigned long size,
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unsigned long offset);
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extern int __find_next_bit(const void *addr, unsigned long size,
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unsigned long offset);
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#define find_next_zero_bit(addr, size, offset) \
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__find_next_zero_bit((addr), (size), (offset))
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#define find_next_bit(addr, size, offset) \
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__find_next_bit((addr), (size), (offset))
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/*
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* The optimizer actually does good code for this case..
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*/
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#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
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#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
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#ifdef __KERNEL__
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#define __clear_bit(nr, addr) clear_bit(nr, addr)
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#define ext2_set_bit test_and_set_bit
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#define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a)
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#define ext2_clear_bit test_and_clear_bit
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#define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a)
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#define ext2_test_bit test_bit
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#define ext2_find_first_zero_bit find_first_zero_bit
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#define ext2_find_next_zero_bit find_next_zero_bit
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/* Bitmap functions for the minix filesystem. */
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#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
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#define minix_set_bit(nr,addr) set_bit(nr,addr)
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#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
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#define minix_test_bit(nr,addr) test_bit(nr,addr)
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#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
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static inline int
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sched_find_first_bit (unsigned long *b)
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{
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if (unlikely(b[0]))
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return __ffs(b[0]);
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if (unlikely(b[1]))
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return 64 + __ffs(b[1]);
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return __ffs(b[2]) + 128;
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_IA64_BITOPS_H */
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