297 lines
8.2 KiB
C
297 lines
8.2 KiB
C
/*
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* linux/arch/arm/mach-omap2/mcbsp.c
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*
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* Copyright (C) 2008 Instituto Nokia de Tecnologia
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* Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Multichannel mode not supported.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <mach/irqs.h>
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#include <plat/dma.h>
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#include <plat/cpu.h>
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#include <plat/mcbsp.h>
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#include "control.h"
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/* McBSP internal signal muxing functions */
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void omap2_mcbsp1_mux_clkr_src(u8 mux)
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{
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u32 v;
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v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
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if (mux == CLKR_SRC_CLKR)
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v &= ~OMAP2_MCBSP1_CLKR_MASK;
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else if (mux == CLKR_SRC_CLKX)
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v |= OMAP2_MCBSP1_CLKR_MASK;
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omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
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}
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EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
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void omap2_mcbsp1_mux_fsr_src(u8 mux)
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{
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u32 v;
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v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
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if (mux == FSR_SRC_FSR)
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v &= ~OMAP2_MCBSP1_FSR_MASK;
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else if (mux == FSR_SRC_FSX)
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v |= OMAP2_MCBSP1_FSR_MASK;
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omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
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}
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EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
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/* McBSP CLKS source switching function */
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int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
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{
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struct omap_mcbsp *mcbsp;
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struct clk *fck_src;
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char *fck_src_name;
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int r;
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if (!omap_mcbsp_check_valid_id(id)) {
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pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
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return -EINVAL;
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}
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mcbsp = id_to_mcbsp_ptr(id);
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if (fck_src_id == MCBSP_CLKS_PAD_SRC)
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fck_src_name = "pad_fck";
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else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
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fck_src_name = "prcm_fck";
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else
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return -EINVAL;
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fck_src = clk_get(mcbsp->dev, fck_src_name);
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if (IS_ERR_OR_NULL(fck_src)) {
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pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
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fck_src_name);
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return -EINVAL;
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}
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clk_disable(mcbsp->fclk);
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r = clk_set_parent(mcbsp->fclk, fck_src);
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if (IS_ERR_VALUE(r)) {
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pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
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"clks", fck_src_name);
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clk_put(fck_src);
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return -EINVAL;
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}
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clk_enable(mcbsp->fclk);
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clk_put(fck_src);
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return 0;
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}
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EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
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/* Platform data */
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#ifdef CONFIG_ARCH_OMAP2420
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static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
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{
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.phys_base = OMAP24XX_MCBSP1_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
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.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
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},
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{
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.phys_base = OMAP24XX_MCBSP2_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
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.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
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},
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};
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#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
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#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
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#else
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#define omap2420_mcbsp_pdata NULL
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#define OMAP2420_MCBSP_PDATA_SZ 0
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#define OMAP2420_MCBSP_REG_NUM 0
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#endif
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#ifdef CONFIG_ARCH_OMAP2430
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static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
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{
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.phys_base = OMAP24XX_MCBSP1_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
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.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
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},
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{
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.phys_base = OMAP24XX_MCBSP2_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
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.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
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},
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{
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.phys_base = OMAP2430_MCBSP3_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
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.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
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},
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{
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.phys_base = OMAP2430_MCBSP4_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
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.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
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},
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{
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.phys_base = OMAP2430_MCBSP5_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
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.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
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},
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};
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#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
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#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
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#else
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#define omap2430_mcbsp_pdata NULL
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#define OMAP2430_MCBSP_PDATA_SZ 0
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#define OMAP2430_MCBSP_REG_NUM 0
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
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{
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.phys_base = OMAP34XX_MCBSP1_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
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.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
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.buffer_size = 0x80, /* The FIFO has 128 locations */
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},
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{
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.phys_base = OMAP34XX_MCBSP2_BASE,
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.phys_base_st = OMAP34XX_MCBSP2_ST_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
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.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
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.buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
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},
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{
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.phys_base = OMAP34XX_MCBSP3_BASE,
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.phys_base_st = OMAP34XX_MCBSP3_ST_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
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.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
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.buffer_size = 0x80, /* The FIFO has 128 locations */
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},
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{
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.phys_base = OMAP34XX_MCBSP4_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
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.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
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.buffer_size = 0x80, /* The FIFO has 128 locations */
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},
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{
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.phys_base = OMAP34XX_MCBSP5_BASE,
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.dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
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.dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
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.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
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.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
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.buffer_size = 0x80, /* The FIFO has 128 locations */
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},
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};
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#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
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#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
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#else
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#define omap34xx_mcbsp_pdata NULL
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#define OMAP34XX_MCBSP_PDATA_SZ 0
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#define OMAP34XX_MCBSP_REG_NUM 0
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#endif
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static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
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{
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.phys_base = OMAP44XX_MCBSP1_BASE,
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.dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
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.dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
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.tx_irq = OMAP44XX_IRQ_MCBSP1,
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},
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{
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.phys_base = OMAP44XX_MCBSP2_BASE,
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.dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
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.dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
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.tx_irq = OMAP44XX_IRQ_MCBSP2,
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},
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{
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.phys_base = OMAP44XX_MCBSP3_BASE,
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.dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
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.dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
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.tx_irq = OMAP44XX_IRQ_MCBSP3,
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},
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{
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.phys_base = OMAP44XX_MCBSP4_BASE,
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.dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
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.dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
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.tx_irq = OMAP44XX_IRQ_MCBSP4,
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},
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};
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#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
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#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
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static int __init omap2_mcbsp_init(void)
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{
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if (cpu_is_omap2420()) {
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omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
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omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
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} else if (cpu_is_omap2430()) {
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omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
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omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
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} else if (cpu_is_omap34xx()) {
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omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
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omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
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} else if (cpu_is_omap44xx()) {
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omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
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omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
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}
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mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
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GFP_KERNEL);
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if (!mcbsp_ptr)
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return -ENOMEM;
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if (cpu_is_omap2420())
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omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
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OMAP2420_MCBSP_PDATA_SZ);
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if (cpu_is_omap2430())
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omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
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OMAP2430_MCBSP_PDATA_SZ);
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if (cpu_is_omap34xx())
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omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
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OMAP34XX_MCBSP_PDATA_SZ);
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if (cpu_is_omap44xx())
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omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
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OMAP44XX_MCBSP_PDATA_SZ);
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return omap_mcbsp_init();
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}
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arch_initcall(omap2_mcbsp_init);
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