128 lines
4.0 KiB
Plaintext
128 lines
4.0 KiB
Plaintext
* Freescale 83xx DMA Controller
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Freescale PowerPC 83xx have on chip general purpose DMA controllers.
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Required properties:
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- compatible : compatible list, contains 2 entries, first is
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"fsl,CHIP-dma", where CHIP is the processor
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(mpc8349, mpc8360, etc.) and the second is
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"fsl,elo-dma"
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- reg : <registers mapping for DMA general status reg>
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- ranges : Should be defined as specified in 1) to describe the
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DMA controller channels.
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- cell-index : controller index. 0 for controller @ 0x8100
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- interrupts : <interrupt mapping for DMA IRQ>
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- interrupt-parent : optional, if needed for interrupt mapping
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- DMA channel nodes:
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- compatible : compatible list, contains 2 entries, first is
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"fsl,CHIP-dma-channel", where CHIP is the processor
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(mpc8349, mpc8350, etc.) and the second is
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"fsl,elo-dma-channel"
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- reg : <registers mapping for channel>
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- cell-index : dma channel index starts at 0.
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Optional properties:
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- interrupts : <interrupt mapping for DMA channel IRQ>
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(on 83xx this is expected to be identical to
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the interrupts property of the parent node)
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- interrupt-parent : optional, if needed for interrupt mapping
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Example:
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
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reg = <82a8 4>;
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ranges = <0 8100 1a4>;
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interrupt-parent = <&ipic>;
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interrupts = <47 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <0>;
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reg = <0 80>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <1>;
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reg = <80 80>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <2>;
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reg = <100 80>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
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cell-index = <3>;
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reg = <180 80>;
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};
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};
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* Freescale 85xx/86xx DMA Controller
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Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
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Required properties:
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- compatible : compatible list, contains 2 entries, first is
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"fsl,CHIP-dma", where CHIP is the processor
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(mpc8540, mpc8540, etc.) and the second is
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"fsl,eloplus-dma"
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- reg : <registers mapping for DMA general status reg>
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- cell-index : controller index. 0 for controller @ 0x21000,
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1 for controller @ 0xc000
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- ranges : Should be defined as specified in 1) to describe the
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DMA controller channels.
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- DMA channel nodes:
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- compatible : compatible list, contains 2 entries, first is
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"fsl,CHIP-dma-channel", where CHIP is the processor
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(mpc8540, mpc8560, etc.) and the second is
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"fsl,eloplus-dma-channel"
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- cell-index : dma channel index starts at 0.
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- reg : <registers mapping for channel>
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- interrupts : <interrupt mapping for DMA channel IRQ>
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- interrupt-parent : optional, if needed for interrupt mapping
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Example:
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
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reg = <21300 4>;
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ranges = <0 21100 200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <0 80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <14 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <80 80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <15 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <100 80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
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reg = <180 80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <17 2>;
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};
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};
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