185aed7557
With the PMB enabled, only P1SEG and up are covered by the PMB mappings, meaning that situations where out-of-bounds physical addresses are read from will lead to TLB reset after the PMB miss, allowing for use cases like dd if=/dev/mem to reset the TLB. Fix this up to make sure the reference is between __MEMORY_START (phys) and __pa(high_memory). This is coherent across all variants of sh/sh64 with and without MMU, though the PMB bug itself is only applicable to SH-4A parts. Reported-by: Hideo Saito <saito@densan.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org> |
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| .. | ||
| asm | ||
| cpu-common/cpu | ||
| cpu-sh2/cpu | ||
| cpu-sh2a/cpu | ||
| cpu-sh3/cpu | ||
| cpu-sh4/cpu | ||
| cpu-sh5/cpu | ||
| mach-common/mach | ||
| mach-dreamcast/mach | ||
| mach-landisk/mach | ||
| mach-se/mach | ||
| mach-sh03/mach | ||