394 lines
9.5 KiB
C
394 lines
9.5 KiB
C
/*
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* Marvell Armada CP110 System Controller
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*
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* Copyright (C) 2016 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/*
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* CP110 has 5 core clocks:
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*
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* - APLL (1 Ghz)
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* - PPv2 core (1/3 APLL)
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* - EIP (1/2 APLL)
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* - Core (1/2 EIP)
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*
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* - NAND clock, which is either:
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* - Equal to the core clock
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* - 2/5 APLL
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*
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* CP110 has 32 gatable clocks, for the various peripherals in the
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* IP. They have fairly complicated parent/child relationships.
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*/
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#define pr_fmt(fmt) "cp110-system-controller: " fmt
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#define CP110_PM_CLOCK_GATING_REG 0x220
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#define CP110_NAND_FLASH_CLK_CTRL_REG 0x700
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#define NF_CLOCK_SEL_400_MASK BIT(0)
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enum {
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CP110_CLK_TYPE_CORE,
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CP110_CLK_TYPE_GATABLE,
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};
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#define CP110_MAX_CORE_CLOCKS 5
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#define CP110_MAX_GATABLE_CLOCKS 32
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#define CP110_CLK_NUM \
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(CP110_MAX_CORE_CLOCKS + CP110_MAX_GATABLE_CLOCKS)
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#define CP110_CORE_APLL 0
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#define CP110_CORE_PPV2 1
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#define CP110_CORE_EIP 2
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#define CP110_CORE_CORE 3
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#define CP110_CORE_NAND 4
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/* A number of gatable clocks need special handling */
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#define CP110_GATE_AUDIO 0
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#define CP110_GATE_COMM_UNIT 1
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#define CP110_GATE_NAND 2
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#define CP110_GATE_PPV2 3
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#define CP110_GATE_SDIO 4
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#define CP110_GATE_MG 5
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#define CP110_GATE_MG_CORE 6
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#define CP110_GATE_XOR1 7
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#define CP110_GATE_XOR0 8
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#define CP110_GATE_GOP_DP 9
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#define CP110_GATE_PCIE_X1_0 11
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#define CP110_GATE_PCIE_X1_1 12
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#define CP110_GATE_PCIE_X4 13
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#define CP110_GATE_PCIE_XOR 14
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#define CP110_GATE_SATA 15
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#define CP110_GATE_SATA_USB 16
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#define CP110_GATE_MAIN 17
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#define CP110_GATE_SDMMC_GOP 18
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#define CP110_GATE_SLOW_IO 21
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#define CP110_GATE_USB3H0 22
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#define CP110_GATE_USB3H1 23
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#define CP110_GATE_USB3DEV 24
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#define CP110_GATE_EIP150 25
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#define CP110_GATE_EIP197 26
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struct cp110_gate_clk {
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struct clk_hw hw;
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struct regmap *regmap;
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u8 bit_idx;
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};
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#define to_cp110_gate_clk(hw) container_of(hw, struct cp110_gate_clk, hw)
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static int cp110_gate_enable(struct clk_hw *hw)
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{
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struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
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regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
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BIT(gate->bit_idx), BIT(gate->bit_idx));
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return 0;
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}
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static void cp110_gate_disable(struct clk_hw *hw)
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{
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struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
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regmap_update_bits(gate->regmap, CP110_PM_CLOCK_GATING_REG,
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BIT(gate->bit_idx), 0);
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}
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static int cp110_gate_is_enabled(struct clk_hw *hw)
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{
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struct cp110_gate_clk *gate = to_cp110_gate_clk(hw);
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u32 val;
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regmap_read(gate->regmap, CP110_PM_CLOCK_GATING_REG, &val);
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return val & BIT(gate->bit_idx);
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}
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static const struct clk_ops cp110_gate_ops = {
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.enable = cp110_gate_enable,
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.disable = cp110_gate_disable,
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.is_enabled = cp110_gate_is_enabled,
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};
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static struct clk_hw *cp110_register_gate(const char *name,
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const char *parent_name,
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struct regmap *regmap, u8 bit_idx)
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{
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struct cp110_gate_clk *gate;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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memset(&init, 0, sizeof(init));
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init.name = name;
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init.ops = &cp110_gate_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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gate->regmap = regmap;
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gate->bit_idx = bit_idx;
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gate->hw.init = &init;
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hw = &gate->hw;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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kfree(gate);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void cp110_unregister_gate(struct clk_hw *hw)
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{
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clk_hw_unregister(hw);
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kfree(to_cp110_gate_clk(hw));
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}
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static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
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void *data)
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{
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struct clk_hw_onecell_data *clk_data = data;
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unsigned int type = clkspec->args[0];
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unsigned int idx = clkspec->args[1];
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if (type == CP110_CLK_TYPE_CORE) {
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if (idx > CP110_MAX_CORE_CLOCKS)
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return ERR_PTR(-EINVAL);
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return clk_data->hws[idx];
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} else if (type == CP110_CLK_TYPE_GATABLE) {
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if (idx > CP110_MAX_GATABLE_CLOCKS)
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return ERR_PTR(-EINVAL);
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return clk_data->hws[CP110_MAX_CORE_CLOCKS + idx];
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}
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return ERR_PTR(-EINVAL);
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}
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static int cp110_syscon_clk_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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struct device_node *np = pdev->dev.of_node;
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const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name;
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struct clk_hw_onecell_data *cp110_clk_data;
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struct clk_hw *hw, **cp110_clks;
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u32 nand_clk_ctrl;
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int i, ret;
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regmap = syscon_node_to_regmap(np);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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ret = regmap_read(regmap, CP110_NAND_FLASH_CLK_CTRL_REG,
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&nand_clk_ctrl);
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if (ret)
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return ret;
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cp110_clk_data = devm_kzalloc(&pdev->dev, sizeof(*cp110_clk_data) +
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sizeof(struct clk_hw *) * CP110_CLK_NUM,
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GFP_KERNEL);
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if (!cp110_clk_data)
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return -ENOMEM;
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cp110_clks = cp110_clk_data->hws;
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cp110_clk_data->num = CP110_CLK_NUM;
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/* Register the APLL which is the root of the hw tree */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_APLL, &apll_name);
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hw = clk_hw_register_fixed_rate(NULL, apll_name, NULL, 0,
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1000 * 1000 * 1000);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail0;
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}
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cp110_clks[CP110_CORE_APLL] = hw;
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/* PPv2 is APLL/3 */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_PPV2, &ppv2_name);
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hw = clk_hw_register_fixed_factor(NULL, ppv2_name, apll_name, 0, 1, 3);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail1;
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}
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cp110_clks[CP110_CORE_PPV2] = hw;
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/* EIP clock is APLL/2 */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_EIP, &eip_name);
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hw = clk_hw_register_fixed_factor(NULL, eip_name, apll_name, 0, 1, 2);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail2;
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}
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cp110_clks[CP110_CORE_EIP] = hw;
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/* Core clock is EIP/2 */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_CORE, &core_name);
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hw = clk_hw_register_fixed_factor(NULL, core_name, eip_name, 0, 1, 2);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail3;
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}
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cp110_clks[CP110_CORE_CORE] = hw;
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/* NAND can be either APLL/2.5 or core clock */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_NAND, &nand_name);
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if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
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hw = clk_hw_register_fixed_factor(NULL, nand_name,
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apll_name, 0, 2, 5);
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else
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hw = clk_hw_register_fixed_factor(NULL, nand_name,
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core_name, 0, 1, 1);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail4;
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}
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cp110_clks[CP110_CORE_NAND] = hw;
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for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
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const char *parent, *name;
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int ret;
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ret = of_property_read_string_index(np,
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"gate-clock-output-names",
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i, &name);
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/* Reached the end of the list? */
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if (ret < 0)
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break;
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if (!strcmp(name, "none"))
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continue;
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switch (i) {
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case CP110_GATE_AUDIO:
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case CP110_GATE_COMM_UNIT:
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case CP110_GATE_EIP150:
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case CP110_GATE_EIP197:
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case CP110_GATE_SLOW_IO:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_MAIN, &parent);
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break;
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case CP110_GATE_MG:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_MG_CORE, &parent);
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break;
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case CP110_GATE_NAND:
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parent = nand_name;
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break;
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case CP110_GATE_PPV2:
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parent = ppv2_name;
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break;
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case CP110_GATE_SDIO:
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case CP110_GATE_GOP_DP:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_SDMMC_GOP, &parent);
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break;
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case CP110_GATE_XOR1:
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case CP110_GATE_XOR0:
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case CP110_GATE_PCIE_X1_0:
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case CP110_GATE_PCIE_X1_1:
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case CP110_GATE_PCIE_X4:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_PCIE_XOR, &parent);
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break;
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case CP110_GATE_SATA:
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case CP110_GATE_USB3H0:
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case CP110_GATE_USB3H1:
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case CP110_GATE_USB3DEV:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_SATA_USB, &parent);
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break;
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default:
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parent = core_name;
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break;
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}
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hw = cp110_register_gate(name, parent, regmap, i);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail_gate;
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}
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cp110_clks[CP110_MAX_CORE_CLOCKS + i] = hw;
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}
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ret = of_clk_add_hw_provider(np, cp110_of_clk_get, cp110_clk_data);
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if (ret)
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goto fail_clk_add;
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platform_set_drvdata(pdev, cp110_clks);
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return 0;
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fail_clk_add:
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fail_gate:
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for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
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hw = cp110_clks[CP110_MAX_CORE_CLOCKS + i];
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if (hw)
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cp110_unregister_gate(hw);
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}
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
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fail4:
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
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fail3:
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_EIP]);
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fail2:
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
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fail1:
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clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_APLL]);
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fail0:
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return ret;
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}
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static const struct of_device_id cp110_syscon_of_match[] = {
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{ .compatible = "marvell,cp110-system-controller0", },
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{ }
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};
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static struct platform_driver cp110_syscon_driver = {
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.probe = cp110_syscon_clk_probe,
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.driver = {
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.name = "marvell-cp110-system-controller0",
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.of_match_table = cp110_syscon_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(cp110_syscon_driver);
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