da4a1efab8
Add the 120MHz refernce clock case for PCH DPLLs. Also determine the reference clock frequency more accurately by checking for the PLLB_REF_INPUT_SPREADSPECTRUMIN refclk input mode. The gen2 code already checked it, but it stil assumed a fixed 66MHz refclk. Instead we need to consult the VBT for the real value. v2: Fix refclk for SSC panel case Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
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| drm | ||
| host1x | ||
| vga | ||
| Makefile | ||