353 lines
9.6 KiB
C
353 lines
9.6 KiB
C
/* blz1230.c: Driver for Blizzard 1230 SCSI IV Controller.
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*
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* Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
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*
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* This driver is based on the CyberStorm driver, hence the occasional
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* reference to CyberStorm.
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*/
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/* TODO:
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*
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* 1) Figure out how to make a cleaner merge with the sparc driver with regard
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* to the caches and the Sparc MMU mapping.
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* 2) Make as few routines required outside the generic driver. A lot of the
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* routines in this file used to be inline!
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/blkdev.h>
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#include <linux/proc_fs.h>
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#include <linux/stat.h>
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#include <linux/interrupt.h>
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#include "scsi.h"
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#include <scsi/scsi_host.h>
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#include "NCR53C9x.h"
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#include <linux/zorro.h>
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#include <asm/irq.h>
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#include <asm/amigaints.h>
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#include <asm/amigahw.h>
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#include <asm/pgtable.h>
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#define MKIV 1
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/* The controller registers can be found in the Z2 config area at these
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* offsets:
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*/
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#define BLZ1230_ESP_ADDR 0x8000
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#define BLZ1230_DMA_ADDR 0x10000
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#define BLZ1230II_ESP_ADDR 0x10000
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#define BLZ1230II_DMA_ADDR 0x10021
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/* The Blizzard 1230 DMA interface
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* Only two things can be programmed in the Blizzard DMA:
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* 1) The data direction is controlled by the status of bit 31 (1 = write)
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* 2) The source/dest address (word aligned, shifted one right) in bits 30-0
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*
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* Program DMA by first latching the highest byte of the address/direction
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* (i.e. bits 31-24 of the long word constructed as described in steps 1+2
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* above). Then write each byte of the address/direction (starting with the
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* top byte, working down) to the DMA address register.
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*
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* Figure out interrupt status by reading the ESP status byte.
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*/
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struct blz1230_dma_registers {
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volatile unsigned char dma_addr; /* DMA address [0x0000] */
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unsigned char dmapad2[0x7fff];
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volatile unsigned char dma_latch; /* DMA latch [0x8000] */
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};
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struct blz1230II_dma_registers {
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volatile unsigned char dma_addr; /* DMA address [0x0000] */
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unsigned char dmapad2[0xf];
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volatile unsigned char dma_latch; /* DMA latch [0x0010] */
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};
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#define BLZ1230_DMA_WRITE 0x80000000
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static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
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static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
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static void dma_dump_state(struct NCR_ESP *esp);
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static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
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static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
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static void dma_ints_off(struct NCR_ESP *esp);
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static void dma_ints_on(struct NCR_ESP *esp);
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static int dma_irq_p(struct NCR_ESP *esp);
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static int dma_ports_p(struct NCR_ESP *esp);
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static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
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static volatile unsigned char cmd_buffer[16];
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/* This is where all commands are put
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* before they are transferred to the ESP chip
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* via PIO.
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*/
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/***************************************************************** Detection */
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int __init blz1230_esp_detect(struct scsi_host_template *tpnt)
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{
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struct NCR_ESP *esp;
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struct zorro_dev *z = NULL;
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unsigned long address;
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struct ESP_regs *eregs;
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unsigned long board;
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#if MKIV
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#define REAL_BLZ1230_ID ZORRO_PROD_PHASE5_BLIZZARD_1230_IV_1260
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#define REAL_BLZ1230_ESP_ADDR BLZ1230_ESP_ADDR
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#define REAL_BLZ1230_DMA_ADDR BLZ1230_DMA_ADDR
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#else
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#define REAL_BLZ1230_ID ZORRO_PROD_PHASE5_BLIZZARD_1230_II_FASTLANE_Z3_CYBERSCSI_CYBERSTORM060
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#define REAL_BLZ1230_ESP_ADDR BLZ1230II_ESP_ADDR
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#define REAL_BLZ1230_DMA_ADDR BLZ1230II_DMA_ADDR
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#endif
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if ((z = zorro_find_device(REAL_BLZ1230_ID, z))) {
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board = z->resource.start;
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if (request_mem_region(board+REAL_BLZ1230_ESP_ADDR,
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sizeof(struct ESP_regs), "NCR53C9x")) {
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/* Do some magic to figure out if the blizzard is
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* equipped with a SCSI controller
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*/
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address = ZTWO_VADDR(board);
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eregs = (struct ESP_regs *)(address + REAL_BLZ1230_ESP_ADDR);
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esp = esp_allocate(tpnt, (void *)board+REAL_BLZ1230_ESP_ADDR);
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esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE | 7));
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udelay(5);
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if(esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE | 7))
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goto err_out;
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/* Do command transfer with programmed I/O */
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esp->do_pio_cmds = 1;
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/* Required functions */
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esp->dma_bytes_sent = &dma_bytes_sent;
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esp->dma_can_transfer = &dma_can_transfer;
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esp->dma_dump_state = &dma_dump_state;
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esp->dma_init_read = &dma_init_read;
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esp->dma_init_write = &dma_init_write;
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esp->dma_ints_off = &dma_ints_off;
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esp->dma_ints_on = &dma_ints_on;
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esp->dma_irq_p = &dma_irq_p;
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esp->dma_ports_p = &dma_ports_p;
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esp->dma_setup = &dma_setup;
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/* Optional functions */
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esp->dma_barrier = 0;
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esp->dma_drain = 0;
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esp->dma_invalidate = 0;
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esp->dma_irq_entry = 0;
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esp->dma_irq_exit = 0;
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esp->dma_led_on = 0;
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esp->dma_led_off = 0;
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esp->dma_poll = 0;
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esp->dma_reset = 0;
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/* SCSI chip speed */
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esp->cfreq = 40000000;
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/* The DMA registers on the Blizzard are mapped
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* relative to the device (i.e. in the same Zorro
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* I/O block).
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*/
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esp->dregs = (void *)(address + REAL_BLZ1230_DMA_ADDR);
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/* ESP register base */
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esp->eregs = eregs;
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/* Set the command buffer */
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esp->esp_command = cmd_buffer;
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esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
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esp->irq = IRQ_AMIGA_PORTS;
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esp->slot = board+REAL_BLZ1230_ESP_ADDR;
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if (request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED,
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"Blizzard 1230 SCSI IV", esp->ehost))
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goto err_out;
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/* Figure out our scsi ID on the bus */
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esp->scsi_id = 7;
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/* We don't have a differential SCSI-bus. */
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esp->diff = 0;
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esp_initialize(esp);
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printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
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esps_running = esps_in_use;
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return esps_in_use;
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}
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}
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return 0;
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err_out:
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scsi_unregister(esp->ehost);
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esp_deallocate(esp);
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release_mem_region(board+REAL_BLZ1230_ESP_ADDR,
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sizeof(struct ESP_regs));
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return 0;
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}
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/************************************************************* DMA Functions */
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static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
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{
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/* Since the Blizzard DMA is fully dedicated to the ESP chip,
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* the number of bytes sent (to the ESP chip) equals the number
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* of bytes in the FIFO - there is no buffering in the DMA controller.
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* XXXX Do I read this right? It is from host to ESP, right?
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*/
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return fifo_count;
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}
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static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
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{
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/* I don't think there's any limit on the Blizzard DMA. So we use what
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* the ESP chip can handle (24 bit).
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*/
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unsigned long sz = sp->SCp.this_residual;
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if(sz > 0x1000000)
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sz = 0x1000000;
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return sz;
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}
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static void dma_dump_state(struct NCR_ESP *esp)
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{
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ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
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amiga_custom.intreqr, amiga_custom.intenar));
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}
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void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
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{
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#if MKIV
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struct blz1230_dma_registers *dregs =
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(struct blz1230_dma_registers *) (esp->dregs);
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#else
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struct blz1230II_dma_registers *dregs =
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(struct blz1230II_dma_registers *) (esp->dregs);
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#endif
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cache_clear(addr, length);
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addr >>= 1;
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addr &= ~(BLZ1230_DMA_WRITE);
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/* First set latch */
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dregs->dma_latch = (addr >> 24) & 0xff;
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/* Then pump the address to the DMA address register */
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#if MKIV
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dregs->dma_addr = (addr >> 24) & 0xff;
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#endif
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dregs->dma_addr = (addr >> 16) & 0xff;
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dregs->dma_addr = (addr >> 8) & 0xff;
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dregs->dma_addr = (addr ) & 0xff;
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}
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void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
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{
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#if MKIV
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struct blz1230_dma_registers *dregs =
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(struct blz1230_dma_registers *) (esp->dregs);
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#else
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struct blz1230II_dma_registers *dregs =
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(struct blz1230II_dma_registers *) (esp->dregs);
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#endif
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cache_push(addr, length);
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addr >>= 1;
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addr |= BLZ1230_DMA_WRITE;
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/* First set latch */
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dregs->dma_latch = (addr >> 24) & 0xff;
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/* Then pump the address to the DMA address register */
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#if MKIV
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dregs->dma_addr = (addr >> 24) & 0xff;
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#endif
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dregs->dma_addr = (addr >> 16) & 0xff;
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dregs->dma_addr = (addr >> 8) & 0xff;
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dregs->dma_addr = (addr ) & 0xff;
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}
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static void dma_ints_off(struct NCR_ESP *esp)
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{
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disable_irq(esp->irq);
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}
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static void dma_ints_on(struct NCR_ESP *esp)
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{
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enable_irq(esp->irq);
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}
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static int dma_irq_p(struct NCR_ESP *esp)
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{
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return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
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}
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static int dma_ports_p(struct NCR_ESP *esp)
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{
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return ((amiga_custom.intenar) & IF_PORTS);
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}
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static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
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{
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/* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
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* so when (write) is true, it actually means READ!
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*/
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if(write){
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dma_init_read(esp, addr, count);
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} else {
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dma_init_write(esp, addr, count);
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}
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}
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#define HOSTS_C
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int blz1230_esp_release(struct Scsi_Host *instance)
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{
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#ifdef MODULE
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unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
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esp_deallocate((struct NCR_ESP *)instance->hostdata);
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esp_release();
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release_mem_region(address, sizeof(struct ESP_regs));
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free_irq(IRQ_AMIGA_PORTS, esp_intr);
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#endif
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return 1;
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}
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static struct scsi_host_template driver_template = {
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.proc_name = "esp-blz1230",
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.proc_info = esp_proc_info,
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.name = "Blizzard1230 SCSI IV",
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.detect = blz1230_esp_detect,
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.slave_alloc = esp_slave_alloc,
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.slave_destroy = esp_slave_destroy,
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.release = blz1230_esp_release,
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.queuecommand = esp_queue,
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.eh_abort_handler = esp_abort,
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.eh_bus_reset_handler = esp_reset,
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.can_queue = 7,
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.this_id = 7,
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.sg_tablesize = SG_ALL,
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.cmd_per_lun = 1,
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.use_clustering = ENABLE_CLUSTERING
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};
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#include "scsi_module.c"
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MODULE_LICENSE("GPL");
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