309 lines
8.4 KiB
C
309 lines
8.4 KiB
C
/*
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*
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* OMAP SRAM detection and management
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*
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* Copyright (C) 2005 Nokia Corporation
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* Written by Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2009-2012 Texas Instruments
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* Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/fncpy.h>
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#include <asm/tlb.h>
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#include <asm/cacheflush.h>
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#include <asm/mach/map.h>
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#include "soc.h"
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#include "iomap.h"
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#include "prm2xxx_3xxx.h"
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#include "sdrc.h"
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#include "sram.h"
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#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
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#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
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#ifdef CONFIG_OMAP4_ERRATA_I688
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#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
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#else
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#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
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#endif
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#define OMAP5_SRAM_PA 0x40300000
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#define SRAM_BOOTLOADER_SZ 0x00
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#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
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#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
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#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
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#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
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#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
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#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
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#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
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#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
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#define GP_DEVICE 0x300
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#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
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static unsigned long omap_sram_start;
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static unsigned long omap_sram_skip;
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static unsigned long omap_sram_size;
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/*
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* Depending on the target RAMFS firewall setup, the public usable amount of
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* SRAM varies. The default accessible size for all device types is 2k. A GP
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* device allows ARM11 but not other initiators for full size. This
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* functionality seems ok until some nice security API happens.
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*/
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static int is_sram_locked(void)
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{
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if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
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/* RAMFW: R/W access to all initiators for all qualifier sets */
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if (cpu_is_omap242x()) {
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writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
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writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
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writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
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}
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if (cpu_is_omap34xx()) {
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writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
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writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
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writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
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writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
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writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
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}
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return 0;
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} else
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return 1; /* assume locked with no PPA or security driver */
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}
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/*
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* The amount of SRAM depends on the core type.
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* Note that we cannot try to test for SRAM here because writes
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* to secure SRAM will hang the system. Also the SRAM is not
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* yet mapped at this point.
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*/
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static void __init omap_detect_sram(void)
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{
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omap_sram_skip = SRAM_BOOTLOADER_SZ;
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if (is_sram_locked()) {
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if (cpu_is_omap34xx()) {
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omap_sram_start = OMAP3_SRAM_PUB_PA;
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if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
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(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
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omap_sram_size = 0x7000; /* 28K */
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omap_sram_skip += SZ_16K;
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} else {
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omap_sram_size = 0x8000; /* 32K */
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}
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} else if (cpu_is_omap44xx()) {
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omap_sram_start = OMAP4_SRAM_PUB_PA;
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omap_sram_size = 0xa000; /* 40K */
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} else if (soc_is_omap54xx()) {
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omap_sram_start = OMAP5_SRAM_PA;
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omap_sram_size = SZ_128K; /* 128KB */
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} else {
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omap_sram_start = OMAP2_SRAM_PUB_PA;
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omap_sram_size = 0x800; /* 2K */
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}
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} else {
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if (soc_is_am33xx()) {
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omap_sram_start = AM33XX_SRAM_PA;
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omap_sram_size = 0x10000; /* 64K */
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} else if (soc_is_am43xx()) {
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omap_sram_start = AM33XX_SRAM_PA;
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omap_sram_size = SZ_256K;
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} else if (cpu_is_omap34xx()) {
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omap_sram_start = OMAP3_SRAM_PA;
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omap_sram_size = 0x10000; /* 64K */
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} else if (cpu_is_omap44xx()) {
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omap_sram_start = OMAP4_SRAM_PA;
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omap_sram_size = 0xe000; /* 56K */
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} else if (soc_is_omap54xx()) {
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omap_sram_start = OMAP5_SRAM_PA;
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omap_sram_size = SZ_128K; /* 128KB */
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} else {
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omap_sram_start = OMAP2_SRAM_PA;
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if (cpu_is_omap242x())
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omap_sram_size = 0xa0000; /* 640K */
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else if (cpu_is_omap243x())
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omap_sram_size = 0x10000; /* 64K */
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}
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}
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}
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/*
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* Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
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*/
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static void __init omap2_map_sram(void)
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{
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int cached = 1;
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#ifdef CONFIG_OMAP4_ERRATA_I688
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if (cpu_is_omap44xx()) {
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omap_sram_start += PAGE_SIZE;
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omap_sram_size -= SZ_16K;
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}
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#endif
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if (cpu_is_omap34xx()) {
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/*
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* SRAM must be marked as non-cached on OMAP3 since the
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* CORE DPLL M2 divider change code (in SRAM) runs with the
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* SDRAM controller disabled, and if it is marked cached,
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* the ARM may attempt to write cache lines back to SDRAM
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* which will cause the system to hang.
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*/
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cached = 0;
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}
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omap_map_sram(omap_sram_start, omap_sram_size,
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omap_sram_skip, cached);
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}
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static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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u32 base_cs, u32 force_unlock);
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void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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u32 base_cs, u32 force_unlock)
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{
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BUG_ON(!_omap2_sram_ddr_init);
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_omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
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base_cs, force_unlock);
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}
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static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
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u32 mem_type);
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void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
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{
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BUG_ON(!_omap2_sram_reprogram_sdrc);
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_omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
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}
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static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
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{
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BUG_ON(!_omap2_set_prcm);
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return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
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}
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#ifdef CONFIG_SOC_OMAP2420
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static int __init omap242x_sram_init(void)
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{
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_omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
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omap242x_sram_ddr_init_sz);
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_omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
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omap242x_sram_reprogram_sdrc_sz);
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_omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
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omap242x_sram_set_prcm_sz);
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return 0;
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}
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#else
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static inline int omap242x_sram_init(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_SOC_OMAP2430
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static int __init omap243x_sram_init(void)
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{
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_omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
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omap243x_sram_ddr_init_sz);
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_omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
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omap243x_sram_reprogram_sdrc_sz);
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_omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
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omap243x_sram_set_prcm_sz);
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return 0;
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}
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#else
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static inline int omap243x_sram_init(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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static u32 (*_omap3_sram_configure_core_dpll)(
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u32 m2, u32 unlock_dll, u32 f, u32 inc,
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u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
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u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
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u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
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{
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BUG_ON(!_omap3_sram_configure_core_dpll);
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return _omap3_sram_configure_core_dpll(
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m2, unlock_dll, f, inc,
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sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
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sdrc_actim_ctrl_b_0, sdrc_mr_0,
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sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
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sdrc_actim_ctrl_b_1, sdrc_mr_1);
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}
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void omap3_sram_restore_context(void)
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{
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omap_sram_reset();
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_omap3_sram_configure_core_dpll =
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omap_sram_push(omap3_sram_configure_core_dpll,
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omap3_sram_configure_core_dpll_sz);
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omap_push_sram_idle();
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}
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static inline int omap34xx_sram_init(void)
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{
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omap3_sram_restore_context();
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return 0;
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}
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#else
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static inline int omap34xx_sram_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_ARCH_OMAP3 */
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static inline int am33xx_sram_init(void)
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{
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return 0;
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}
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int __init omap_sram_init(void)
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{
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omap_detect_sram();
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omap2_map_sram();
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if (cpu_is_omap242x())
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omap242x_sram_init();
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else if (cpu_is_omap2430())
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omap243x_sram_init();
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else if (soc_is_am33xx())
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am33xx_sram_init();
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else if (cpu_is_omap34xx())
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omap34xx_sram_init();
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return 0;
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}
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