444 lines
11 KiB
C
444 lines
11 KiB
C
/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
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* JZ4740 SoC RTC driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/rtc.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define JZ_REG_RTC_CTRL 0x00
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#define JZ_REG_RTC_SEC 0x04
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#define JZ_REG_RTC_SEC_ALARM 0x08
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#define JZ_REG_RTC_REGULATOR 0x0C
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#define JZ_REG_RTC_HIBERNATE 0x20
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#define JZ_REG_RTC_WAKEUP_FILTER 0x24
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#define JZ_REG_RTC_RESET_COUNTER 0x28
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#define JZ_REG_RTC_SCRATCHPAD 0x34
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/* The following are present on the jz4780 */
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#define JZ_REG_RTC_WENR 0x3C
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#define JZ_RTC_WENR_WEN BIT(31)
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#define JZ_RTC_CTRL_WRDY BIT(7)
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#define JZ_RTC_CTRL_1HZ BIT(6)
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#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
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#define JZ_RTC_CTRL_AF BIT(4)
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#define JZ_RTC_CTRL_AF_IRQ BIT(3)
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#define JZ_RTC_CTRL_AE BIT(2)
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#define JZ_RTC_CTRL_ENABLE BIT(0)
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/* Magic value to enable writes on jz4780 */
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#define JZ_RTC_WENR_MAGIC 0xA55A
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#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0
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#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0
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enum jz4740_rtc_type {
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ID_JZ4740,
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ID_JZ4780,
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};
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struct jz4740_rtc {
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void __iomem *base;
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enum jz4740_rtc_type type;
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struct rtc_device *rtc;
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struct clk *clk;
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int irq;
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spinlock_t lock;
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unsigned int min_wakeup_pin_assert_time;
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unsigned int reset_pin_assert_time;
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};
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static struct device *dev_for_power_off;
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static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
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{
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return readl(rtc->base + reg);
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}
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static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
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{
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uint32_t ctrl;
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int timeout = 1000;
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do {
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ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
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} while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
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return timeout ? 0 : -EIO;
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}
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static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
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{
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uint32_t ctrl;
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int ret, timeout = 1000;
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ret = jz4740_rtc_wait_write_ready(rtc);
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if (ret != 0)
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return ret;
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writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
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do {
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ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
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} while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
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return timeout ? 0 : -EIO;
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}
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static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
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uint32_t val)
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{
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int ret = 0;
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if (rtc->type >= ID_JZ4780)
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ret = jz4780_rtc_enable_write(rtc);
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if (ret == 0)
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ret = jz4740_rtc_wait_write_ready(rtc);
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if (ret == 0)
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writel(val, rtc->base + reg);
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return ret;
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}
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static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
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bool set)
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{
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int ret;
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unsigned long flags;
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uint32_t ctrl;
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spin_lock_irqsave(&rtc->lock, flags);
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ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
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/* Don't clear interrupt flags by accident */
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ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
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if (set)
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ctrl |= mask;
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else
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ctrl &= ~mask;
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ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
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spin_unlock_irqrestore(&rtc->lock, flags);
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return ret;
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}
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static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
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{
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struct jz4740_rtc *rtc = dev_get_drvdata(dev);
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uint32_t secs, secs2;
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int timeout = 5;
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/* If the seconds register is read while it is updated, it can contain a
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* bogus value. This can be avoided by making sure that two consecutive
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* reads have the same value.
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*/
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secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
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secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
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while (secs != secs2 && --timeout) {
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secs = secs2;
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secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
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}
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if (timeout == 0)
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return -EIO;
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rtc_time_to_tm(secs, time);
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return rtc_valid_tm(time);
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}
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static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
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{
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struct jz4740_rtc *rtc = dev_get_drvdata(dev);
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return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
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}
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static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct jz4740_rtc *rtc = dev_get_drvdata(dev);
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uint32_t secs;
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uint32_t ctrl;
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secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
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ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
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alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
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alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
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rtc_time_to_tm(secs, &alrm->time);
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return rtc_valid_tm(&alrm->time);
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}
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static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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int ret;
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struct jz4740_rtc *rtc = dev_get_drvdata(dev);
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unsigned long secs;
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rtc_tm_to_time(&alrm->time, &secs);
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ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
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if (!ret)
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ret = jz4740_rtc_ctrl_set_bits(rtc,
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JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
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return ret;
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}
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static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
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{
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struct jz4740_rtc *rtc = dev_get_drvdata(dev);
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return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
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}
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static const struct rtc_class_ops jz4740_rtc_ops = {
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.read_time = jz4740_rtc_read_time,
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.set_mmss = jz4740_rtc_set_mmss,
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.read_alarm = jz4740_rtc_read_alarm,
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.set_alarm = jz4740_rtc_set_alarm,
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.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
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};
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static irqreturn_t jz4740_rtc_irq(int irq, void *data)
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{
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struct jz4740_rtc *rtc = data;
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uint32_t ctrl;
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unsigned long events = 0;
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ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
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if (ctrl & JZ_RTC_CTRL_1HZ)
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events |= (RTC_UF | RTC_IRQF);
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if (ctrl & JZ_RTC_CTRL_AF)
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events |= (RTC_AF | RTC_IRQF);
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rtc_update_irq(rtc->rtc, 1, events);
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jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
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return IRQ_HANDLED;
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}
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static void jz4740_rtc_poweroff(struct device *dev)
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{
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struct jz4740_rtc *rtc = dev_get_drvdata(dev);
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jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
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}
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static void jz4740_rtc_power_off(void)
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{
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struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
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unsigned long rtc_rate;
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unsigned long wakeup_filter_ticks;
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unsigned long reset_counter_ticks;
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clk_prepare_enable(rtc->clk);
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rtc_rate = clk_get_rate(rtc->clk);
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/*
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* Set minimum wakeup pin assertion time: 100 ms.
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* Range is 0 to 2 sec if RTC is clocked at 32 kHz.
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*/
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wakeup_filter_ticks =
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(rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
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if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
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wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
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else
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wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
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jz4740_rtc_reg_write(rtc,
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JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
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/*
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* Set reset pin low-level assertion time after wakeup: 60 ms.
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* Range is 0 to 125 ms if RTC is clocked at 32 kHz.
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*/
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reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
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if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
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reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
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else
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reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
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jz4740_rtc_reg_write(rtc,
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JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
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jz4740_rtc_poweroff(dev_for_power_off);
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machine_halt();
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}
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static const struct of_device_id jz4740_rtc_of_match[] = {
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{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
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{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
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{},
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};
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static int jz4740_rtc_probe(struct platform_device *pdev)
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{
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int ret;
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struct jz4740_rtc *rtc;
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uint32_t scratchpad;
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struct resource *mem;
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const struct platform_device_id *id = platform_get_device_id(pdev);
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const struct of_device_id *of_id = of_match_device(
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jz4740_rtc_of_match, &pdev->dev);
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struct device_node *np = pdev->dev.of_node;
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rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
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if (!rtc)
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return -ENOMEM;
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if (of_id)
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rtc->type = (enum jz4740_rtc_type)of_id->data;
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else
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rtc->type = id->driver_data;
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rtc->irq = platform_get_irq(pdev, 0);
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if (rtc->irq < 0) {
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dev_err(&pdev->dev, "Failed to get platform irq\n");
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return -ENOENT;
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}
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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rtc->base = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(rtc->base))
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return PTR_ERR(rtc->base);
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rtc->clk = devm_clk_get(&pdev->dev, "rtc");
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if (IS_ERR(rtc->clk)) {
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dev_err(&pdev->dev, "Failed to get RTC clock\n");
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return PTR_ERR(rtc->clk);
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}
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spin_lock_init(&rtc->lock);
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platform_set_drvdata(pdev, rtc);
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device_init_wakeup(&pdev->dev, 1);
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rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
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&jz4740_rtc_ops, THIS_MODULE);
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if (IS_ERR(rtc->rtc)) {
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ret = PTR_ERR(rtc->rtc);
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dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
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return ret;
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}
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ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
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pdev->name, rtc);
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if (ret) {
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dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
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return ret;
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}
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scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
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if (scratchpad != 0x12345678) {
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ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
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ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
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if (ret) {
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dev_err(&pdev->dev, "Could not write write to RTC registers\n");
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return ret;
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}
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}
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if (np && of_device_is_system_power_controller(np)) {
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if (!pm_power_off) {
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/* Default: 60ms */
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rtc->reset_pin_assert_time = 60;
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of_property_read_u32(np, "reset-pin-assert-time-ms",
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&rtc->reset_pin_assert_time);
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/* Default: 100ms */
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rtc->min_wakeup_pin_assert_time = 100;
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of_property_read_u32(np,
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"min-wakeup-pin-assert-time-ms",
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&rtc->min_wakeup_pin_assert_time);
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dev_for_power_off = &pdev->dev;
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pm_power_off = jz4740_rtc_power_off;
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} else {
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dev_warn(&pdev->dev,
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"Poweroff handler already present!\n");
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}
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}
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return 0;
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}
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#ifdef CONFIG_PM
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static int jz4740_rtc_suspend(struct device *dev)
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{
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struct jz4740_rtc *rtc = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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enable_irq_wake(rtc->irq);
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return 0;
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}
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static int jz4740_rtc_resume(struct device *dev)
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{
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struct jz4740_rtc *rtc = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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disable_irq_wake(rtc->irq);
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return 0;
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}
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static const struct dev_pm_ops jz4740_pm_ops = {
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.suspend = jz4740_rtc_suspend,
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.resume = jz4740_rtc_resume,
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};
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#define JZ4740_RTC_PM_OPS (&jz4740_pm_ops)
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#else
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#define JZ4740_RTC_PM_OPS NULL
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#endif /* CONFIG_PM */
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static const struct platform_device_id jz4740_rtc_ids[] = {
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{ "jz4740-rtc", ID_JZ4740 },
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{ "jz4780-rtc", ID_JZ4780 },
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{}
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};
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static struct platform_driver jz4740_rtc_driver = {
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.probe = jz4740_rtc_probe,
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.driver = {
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.name = "jz4740-rtc",
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.pm = JZ4740_RTC_PM_OPS,
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.of_match_table = of_match_ptr(jz4740_rtc_of_match),
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},
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.id_table = jz4740_rtc_ids,
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};
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builtin_platform_driver(jz4740_rtc_driver);
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