350 lines
7.8 KiB
C
350 lines
7.8 KiB
C
/*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* stevel@mvista.com or source@mvista.com
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Ethernet driver definitions for the MIPS GT96100 Advanced
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* Communication Controller.
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*
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*/
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#ifndef _GT96100ETH_H
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#define _GT96100ETH_H
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#include <linux/config.h>
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#include <asm/galileo-boards/gt96100.h>
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#define dbg(lvl, format, arg...) \
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if (lvl <= GT96100_DEBUG) \
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printk(KERN_DEBUG "%s: " format, dev->name , ## arg)
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#define err(format, arg...) \
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printk(KERN_ERR "%s: " format, dev->name , ## arg)
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#define info(format, arg...) \
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printk(KERN_INFO "%s: " format, dev->name , ## arg)
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#define warn(format, arg...) \
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printk(KERN_WARNING "%s: " format, dev->name , ## arg)
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/* Keep the ring sizes a power of two for efficiency. */
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#define TX_RING_SIZE 16
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#define RX_RING_SIZE 32
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#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
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#define RX_HASH_TABLE_SIZE 16384
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#define HASH_HOP_NUMBER 12
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#define NUM_INTERFACES 2
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#define GT96100ETH_TX_TIMEOUT HZ/4
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#define GT96100_ETH0_BASE (MIPS_GT96100_BASE + GT96100_ETH_PORT_CONFIG)
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#define GT96100_ETH1_BASE (GT96100_ETH0_BASE + GT96100_ETH_IO_SIZE)
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#ifdef CONFIG_MIPS_EV96100
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#define GT96100_ETHER0_IRQ 3
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#define GT96100_ETHER1_IRQ 4
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#else
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#define GT96100_ETHER0_IRQ -1
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#define GT96100_ETHER1_IRQ -1
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#endif
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#define REV_GT96100 1
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#define REV_GT96100A_1 2
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#define REV_GT96100A 3
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#define GT96100ETH_READ(gp, offset) \
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GT96100_READ((gp->port_offset + offset))
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#define GT96100ETH_WRITE(gp, offset, data) \
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GT96100_WRITE((gp->port_offset + offset), data)
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#define GT96100ETH_SETBIT(gp, offset, bits) {\
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u32 val = GT96100ETH_READ(gp, offset); val |= (u32)(bits); \
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GT96100ETH_WRITE(gp, offset, val); }
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#define GT96100ETH_CLRBIT(gp, offset, bits) {\
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u32 val = GT96100ETH_READ(gp, offset); val &= (u32)(~(bits)); \
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GT96100ETH_WRITE(gp, offset, val); }
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/* Bit definitions of the SMI Reg */
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enum {
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smirDataMask = 0xffff,
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smirPhyAdMask = 0x1f<<16,
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smirPhyAdBit = 16,
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smirRegAdMask = 0x1f<<21,
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smirRegAdBit = 21,
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smirOpCode = 1<<26,
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smirReadValid = 1<<27,
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smirBusy = 1<<28
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};
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/* Bit definitions of the Port Config Reg */
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enum pcr_bits {
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pcrPM = 1,
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pcrRBM = 2,
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pcrPBF = 4,
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pcrEN = 1<<7,
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pcrLPBKMask = 0x3<<8,
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pcrLPBKBit = 8,
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pcrFC = 1<<10,
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pcrHS = 1<<12,
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pcrHM = 1<<13,
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pcrHDM = 1<<14,
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pcrHD = 1<<15,
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pcrISLMask = 0x7<<28,
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pcrISLBit = 28,
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pcrACCS = 1<<31
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};
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/* Bit definitions of the Port Config Extend Reg */
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enum pcxr_bits {
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pcxrIGMP = 1,
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pcxrSPAN = 2,
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pcxrPAR = 4,
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pcxrPRIOtxMask = 0x7<<3,
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pcxrPRIOtxBit = 3,
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pcxrPRIOrxMask = 0x3<<6,
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pcxrPRIOrxBit = 6,
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pcxrPRIOrxOverride = 1<<8,
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pcxrDPLXen = 1<<9,
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pcxrFCTLen = 1<<10,
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pcxrFLP = 1<<11,
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pcxrFCTL = 1<<12,
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pcxrMFLMask = 0x3<<14,
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pcxrMFLBit = 14,
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pcxrMIBclrMode = 1<<16,
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pcxrSpeed = 1<<18,
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pcxrSpeeden = 1<<19,
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pcxrRMIIen = 1<<20,
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pcxrDSCPen = 1<<21
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};
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/* Bit definitions of the Port Command Reg */
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enum pcmr_bits {
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pcmrFJ = 1<<15
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};
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/* Bit definitions of the Port Status Reg */
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enum psr_bits {
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psrSpeed = 1,
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psrDuplex = 2,
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psrFctl = 4,
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psrLink = 8,
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psrPause = 1<<4,
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psrTxLow = 1<<5,
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psrTxHigh = 1<<6,
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psrTxInProg = 1<<7
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};
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/* Bit definitions of the SDMA Config Reg */
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enum sdcr_bits {
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sdcrRCMask = 0xf<<2,
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sdcrRCBit = 2,
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sdcrBLMR = 1<<6,
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sdcrBLMT = 1<<7,
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sdcrPOVR = 1<<8,
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sdcrRIFB = 1<<9,
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sdcrBSZMask = 0x3<<12,
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sdcrBSZBit = 12
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};
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/* Bit definitions of the SDMA Command Reg */
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enum sdcmr_bits {
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sdcmrERD = 1<<7,
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sdcmrAR = 1<<15,
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sdcmrSTDH = 1<<16,
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sdcmrSTDL = 1<<17,
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sdcmrTXDH = 1<<23,
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sdcmrTXDL = 1<<24,
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sdcmrAT = 1<<31
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};
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/* Bit definitions of the Interrupt Cause Reg */
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enum icr_bits {
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icrRxBuffer = 1,
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icrTxBufferHigh = 1<<2,
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icrTxBufferLow = 1<<3,
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icrTxEndHigh = 1<<6,
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icrTxEndLow = 1<<7,
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icrRxError = 1<<8,
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icrTxErrorHigh = 1<<10,
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icrTxErrorLow = 1<<11,
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icrRxOVR = 1<<12,
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icrTxUdr = 1<<13,
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icrRxBufferQ0 = 1<<16,
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icrRxBufferQ1 = 1<<17,
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icrRxBufferQ2 = 1<<18,
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icrRxBufferQ3 = 1<<19,
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icrRxErrorQ0 = 1<<20,
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icrRxErrorQ1 = 1<<21,
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icrRxErrorQ2 = 1<<22,
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icrRxErrorQ3 = 1<<23,
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icrMIIPhySTC = 1<<28,
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icrSMIdone = 1<<29,
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icrEtherIntSum = 1<<31
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};
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/* The Rx and Tx descriptor lists. */
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typedef struct {
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#ifdef DESC_BE
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u16 byte_cnt;
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u16 reserved;
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#else
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u16 reserved;
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u16 byte_cnt;
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#endif
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u32 cmdstat;
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u32 next;
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u32 buff_ptr;
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} __attribute__ ((packed)) gt96100_td_t;
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typedef struct {
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#ifdef DESC_BE
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u16 buff_sz;
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u16 byte_cnt;
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#else
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u16 byte_cnt;
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u16 buff_sz;
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#endif
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u32 cmdstat;
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u32 next;
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u32 buff_ptr;
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} __attribute__ ((packed)) gt96100_rd_t;
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/* Values for the Tx command-status descriptor entry. */
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enum td_cmdstat {
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txOwn = 1<<31,
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txAutoMode = 1<<30,
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txEI = 1<<23,
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txGenCRC = 1<<22,
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txPad = 1<<18,
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txFirst = 1<<17,
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txLast = 1<<16,
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txErrorSummary = 1<<15,
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txReTxCntMask = 0x0f<<10,
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txReTxCntBit = 10,
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txCollision = 1<<9,
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txReTxLimit = 1<<8,
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txUnderrun = 1<<6,
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txLateCollision = 1<<5
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};
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/* Values for the Rx command-status descriptor entry. */
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enum rd_cmdstat {
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rxOwn = 1<<31,
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rxAutoMode = 1<<30,
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rxEI = 1<<23,
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rxFirst = 1<<17,
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rxLast = 1<<16,
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rxErrorSummary = 1<<15,
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rxIGMP = 1<<14,
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rxHashExpired = 1<<13,
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rxMissedFrame = 1<<12,
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rxFrameType = 1<<11,
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rxShortFrame = 1<<8,
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rxMaxFrameLen = 1<<7,
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rxOverrun = 1<<6,
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rxCollision = 1<<4,
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rxCRCError = 1
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};
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/* Bit fields of a Hash Table Entry */
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enum hash_table_entry {
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hteValid = 1,
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hteSkip = 2,
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hteRD = 4
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};
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// The MIB counters
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typedef struct {
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u32 byteReceived;
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u32 byteSent;
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u32 framesReceived;
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u32 framesSent;
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u32 totalByteReceived;
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u32 totalFramesReceived;
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u32 broadcastFramesReceived;
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u32 multicastFramesReceived;
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u32 cRCError;
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u32 oversizeFrames;
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u32 fragments;
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u32 jabber;
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u32 collision;
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u32 lateCollision;
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u32 frames64;
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u32 frames65_127;
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u32 frames128_255;
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u32 frames256_511;
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u32 frames512_1023;
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u32 frames1024_MaxSize;
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u32 macRxError;
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u32 droppedFrames;
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u32 outMulticastFrames;
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u32 outBroadcastFrames;
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u32 undersizeFrames;
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} mib_counters_t;
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struct gt96100_private {
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gt96100_rd_t* rx_ring;
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gt96100_td_t* tx_ring;
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// The Rx and Tx rings must be 16-byte aligned
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dma_addr_t rx_ring_dma;
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dma_addr_t tx_ring_dma;
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char* hash_table;
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// The Hash Table must be 8-byte aligned
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dma_addr_t hash_table_dma;
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int hash_mode;
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// The Rx buffers must be 8-byte aligned
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char* rx_buff;
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dma_addr_t rx_buff_dma;
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// Tx buffers (tx_skbuff[i]->data) with less than 8 bytes
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// of payload must be 8-byte aligned
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struct sk_buff* tx_skbuff[TX_RING_SIZE];
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int rx_next_out; /* The next free ring entry to receive */
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int tx_next_in; /* The next free ring entry to send */
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int tx_next_out; /* The last ring entry the ISR processed */
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int tx_count; /* current # of pkts waiting to be sent in Tx ring */
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int intr_work_done; /* number of Rx and Tx pkts processed in the isr */
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int tx_full; /* Tx ring is full */
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mib_counters_t mib;
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struct net_device_stats stats;
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int io_size;
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int port_num; // 0 or 1
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int chip_rev;
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u32 port_offset;
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int phy_addr; // PHY address
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u32 last_psr; // last value of the port status register
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int options; /* User-settable misc. driver options. */
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int drv_flags;
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struct timer_list timer;
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spinlock_t lock; /* Serialise access to device */
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};
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#endif
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