300 lines
8.4 KiB
C
300 lines
8.4 KiB
C
/*
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/gic.h>
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#include <asm/localtimer.h>
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#include <mach/msm_iomap.h>
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#include <mach/cpu.h>
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#include <mach/board.h>
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#define TIMER_MATCH_VAL 0x0000
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#define TIMER_COUNT_VAL 0x0004
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#define TIMER_ENABLE 0x0008
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#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
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#define TIMER_ENABLE_EN BIT(0)
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#define TIMER_CLEAR 0x000C
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#define DGT_CLK_CTL 0x0034
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#define DGT_CLK_CTL_DIV_4 0x3
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#define GPT_HZ 32768
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#define MSM_GLOBAL_TIMER MSM_CLOCK_GPT
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/* TODO: Remove these ifdefs */
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#if defined(CONFIG_ARCH_QSD8X50)
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#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
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#define MSM_DGT_SHIFT (0)
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#elif defined(CONFIG_ARCH_MSM7X30)
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#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
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#define MSM_DGT_SHIFT (0)
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#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
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#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
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#define MSM_DGT_SHIFT (0)
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#else
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#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
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#define MSM_DGT_SHIFT (5)
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#endif
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struct msm_clock {
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struct clock_event_device clockevent;
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struct clocksource clocksource;
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unsigned int irq;
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void __iomem *regbase;
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uint32_t freq;
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uint32_t shift;
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void __iomem *global_counter;
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void __iomem *local_counter;
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union {
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struct clock_event_device *evt;
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struct clock_event_device __percpu **percpu_evt;
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};
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};
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enum {
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MSM_CLOCK_GPT,
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MSM_CLOCK_DGT,
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NR_TIMERS,
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};
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static struct msm_clock msm_clocks[];
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static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
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if (evt->event_handler == NULL)
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return IRQ_HANDLED;
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static cycle_t msm_read_timer_count(struct clocksource *cs)
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{
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struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
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/*
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* Shift timer count down by a constant due to unreliable lower bits
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* on some targets.
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*/
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return readl(clk->global_counter) >> clk->shift;
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}
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static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
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{
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#ifdef CONFIG_SMP
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int i;
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for (i = 0; i < NR_TIMERS; i++)
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if (evt == &(msm_clocks[i].clockevent))
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return &msm_clocks[i];
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return &msm_clocks[MSM_GLOBAL_TIMER];
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#else
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return container_of(evt, struct msm_clock, clockevent);
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#endif
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}
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static int msm_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct msm_clock *clock = clockevent_to_clock(evt);
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uint32_t now = readl(clock->local_counter);
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uint32_t alarm = now + (cycles << clock->shift);
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writel(alarm, clock->regbase + TIMER_MATCH_VAL);
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return 0;
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}
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static void msm_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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struct msm_clock *clock = clockevent_to_clock(evt);
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switch (mode) {
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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writel(0, clock->regbase + TIMER_ENABLE);
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break;
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}
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}
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static struct msm_clock msm_clocks[] = {
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[MSM_CLOCK_GPT] = {
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.clockevent = {
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.name = "gp_timer",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 200,
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.set_next_event = msm_timer_set_next_event,
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.set_mode = msm_timer_set_mode,
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},
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.irq = INT_GP_TIMER_EXP,
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.freq = GPT_HZ,
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},
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[MSM_CLOCK_DGT] = {
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.clocksource = {
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.name = "dg_timer",
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.rating = 300,
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.read = msm_read_timer_count,
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.mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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},
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.freq = DGT_HZ >> MSM_DGT_SHIFT,
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.shift = MSM_DGT_SHIFT,
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}
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};
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static void __init msm_timer_init(void)
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{
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struct msm_clock *clock;
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struct clock_event_device *ce = &msm_clocks[MSM_CLOCK_GPT].clockevent;
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struct clocksource *cs = &msm_clocks[MSM_CLOCK_DGT].clocksource;
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int res;
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int global_offset = 0;
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if (cpu_is_msm7x01()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
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} else if (cpu_is_msm7x30()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
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} else if (cpu_is_qsd8x50()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
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} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
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msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
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/* Use CPU0's timer as the global timer. */
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global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
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} else
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BUG();
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#ifdef CONFIG_ARCH_MSM_SCORPIONMP
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writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
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#endif
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clock = &msm_clocks[MSM_CLOCK_GPT];
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clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
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writel_relaxed(0, clock->regbase + TIMER_ENABLE);
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writel_relaxed(0, clock->regbase + TIMER_CLEAR);
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writel_relaxed(~0, clock->regbase + TIMER_MATCH_VAL);
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ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
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/*
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* allow at least 10 seconds to notice that the timer
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* wrapped
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*/
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ce->max_delta_ns =
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clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
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/* 4 gets rounded down to 3 */
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ce->min_delta_ns = clockevent_delta2ns(4, ce);
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ce->cpumask = cpumask_of(0);
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ce->irq = clock->irq;
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if (cpu_is_msm8x60() || cpu_is_msm8960()) {
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clock->percpu_evt = alloc_percpu(struct clock_event_device *);
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if (!clock->percpu_evt) {
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pr_err("memory allocation failed for %s\n", ce->name);
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goto err;
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}
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*__this_cpu_ptr(clock->percpu_evt) = ce;
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res = request_percpu_irq(ce->irq, msm_timer_interrupt,
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ce->name, clock->percpu_evt);
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if (!res)
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enable_percpu_irq(ce->irq, 0);
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} else {
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clock->evt = ce;
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res = request_irq(ce->irq, msm_timer_interrupt,
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IRQF_TIMER | IRQF_NOBALANCING |
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IRQF_TRIGGER_RISING, ce->name, &clock->evt);
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}
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if (res)
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pr_err("request_irq failed for %s\n", ce->name);
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clockevents_register_device(ce);
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err:
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clock = &msm_clocks[MSM_CLOCK_DGT];
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clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
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clock->global_counter = clock->local_counter + global_offset;
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writel_relaxed(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
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res = clocksource_register_hz(cs, clock->freq);
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if (res)
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pr_err("clocksource_register failed for %s\n", cs->name);
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}
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#ifdef CONFIG_LOCAL_TIMERS
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int __cpuinit local_timer_setup(struct clock_event_device *evt)
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{
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static bool local_timer_inited;
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struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
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/* Use existing clock_event for cpu 0 */
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if (!smp_processor_id())
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return 0;
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if (!local_timer_inited) {
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writel(0, clock->regbase + TIMER_ENABLE);
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writel(0, clock->regbase + TIMER_CLEAR);
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writel(~0, clock->regbase + TIMER_MATCH_VAL);
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local_timer_inited = true;
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}
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evt->irq = clock->irq;
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evt->name = "local_timer";
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evt->features = CLOCK_EVT_FEAT_ONESHOT;
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evt->rating = clock->clockevent.rating;
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evt->set_mode = msm_timer_set_mode;
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evt->set_next_event = msm_timer_set_next_event;
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evt->shift = clock->clockevent.shift;
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evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
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evt->max_delta_ns =
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clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
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evt->min_delta_ns = clockevent_delta2ns(4, evt);
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*__this_cpu_ptr(clock->percpu_evt) = evt;
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enable_percpu_irq(evt->irq, 0);
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clockevents_register_device(evt);
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return 0;
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}
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void local_timer_stop(struct clock_event_device *evt)
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{
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evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
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disable_percpu_irq(evt->irq);
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}
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#endif /* CONFIG_LOCAL_TIMERS */
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struct sys_timer msm_timer = {
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.init = msm_timer_init
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};
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