132 lines
3.5 KiB
C
132 lines
3.5 KiB
C
/*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/system_misc.h>
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#include <asm/proc-fns.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "common.h"
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#include "hardware.h"
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static void __iomem *wdog_base;
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static struct clk *wdog_clk;
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/*
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* Reset the system. It is called by machine_restart().
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*/
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void mxc_restart(enum reboot_mode mode, const char *cmd)
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{
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unsigned int wcr_enable;
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if (!wdog_base)
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goto reset_fallback;
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if (!IS_ERR(wdog_clk))
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clk_enable(wdog_clk);
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if (cpu_is_mx1())
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wcr_enable = (1 << 0);
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else
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wcr_enable = (1 << 2);
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/* Assert SRS signal */
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__raw_writew(wcr_enable, wdog_base);
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/*
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* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
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* written twice), we add another two writes to ensure there must be at
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* least two writes happen in the same one 32kHz clock period. We save
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* the target check here, since the writes shouldn't be a huge burden
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* for other platforms.
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*/
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__raw_writew(wcr_enable, wdog_base);
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__raw_writew(wcr_enable, wdog_base);
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/* wait for reset to assert... */
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mdelay(500);
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pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
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/* delay to allow the serial port to show the message */
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mdelay(50);
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reset_fallback:
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/* we'll take a jump through zero as a poor second */
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soft_restart(0);
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}
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void __init mxc_arch_reset_init(void __iomem *base)
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{
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wdog_base = base;
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wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
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if (IS_ERR(wdog_clk))
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pr_warn("%s: failed to get wdog clock\n", __func__);
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else
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clk_prepare(wdog_clk);
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}
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#ifdef CONFIG_CACHE_L2X0
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void __init imx_init_l2cache(void)
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{
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void __iomem *l2x0_base;
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struct device_node *np;
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unsigned int val;
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np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
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if (!np)
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goto out;
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l2x0_base = of_iomap(np, 0);
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if (!l2x0_base) {
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of_node_put(np);
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goto out;
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}
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/* Configure the L2 PREFETCH and POWER registers */
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val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
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val |= 0x70800000;
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/*
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* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
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* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
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* But according to ARM PL310 errata: 752271
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* ID: 752271: Double linefill feature can cause data corruption
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* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
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* Workaround: The only workaround to this erratum is to disable the
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* double linefill feature. This is the default behavior.
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*/
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if (cpu_is_imx6q())
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val &= ~(1 << 30 | 1 << 23);
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writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
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iounmap(l2x0_base);
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of_node_put(np);
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out:
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l2x0_of_init(0, ~0);
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}
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#endif
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