158 lines
3.7 KiB
C
158 lines
3.7 KiB
C
/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4210 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include "exynos-cpufreq.h"
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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static unsigned int exynos4210_volt_table[] = {
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1250000, 1150000, 1050000, 975000, 950000,
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};
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static struct cpufreq_frequency_table exynos4210_freq_table[] = {
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{L0, 1200 * 1000},
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{L1, 1000 * 1000},
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{L2, 800 * 1000},
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{L3, 500 * 1000},
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{L4, 200 * 1000},
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{0, CPUFREQ_TABLE_END},
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};
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static struct apll_freq apll_freq_4210[] = {
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/*
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* values:
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* freq
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* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
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* clock divider for COPY, HPM, RESERVED
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* PLL M, P, S
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*/
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APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
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APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
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APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
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APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
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APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
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};
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static void exynos4210_set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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/* Change Divider - CPU0 */
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tmp = apll_freq_4210[div_index].clk_div_cpu0;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
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do {
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tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
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} while (tmp & 0x1111111);
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/* Change Divider - CPU1 */
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tmp = apll_freq_4210[div_index].clk_div_cpu1;
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__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
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do {
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tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
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} while (tmp & 0x11);
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}
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static void exynos4210_set_apll(unsigned int index)
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{
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unsigned int tmp, freq = apll_freq_4210[index].freq;
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/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
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>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
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tmp &= 0x7;
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} while (tmp != 0x2);
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clk_set_rate(mout_apll, freq * 1000);
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/* MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
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tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
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} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
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}
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static void exynos4210_set_frequency(unsigned int old_index,
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unsigned int new_index)
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{
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if (old_index > new_index) {
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exynos4210_set_clkdiv(new_index);
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exynos4210_set_apll(new_index);
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} else if (old_index < new_index) {
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exynos4210_set_apll(new_index);
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exynos4210_set_clkdiv(new_index);
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}
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}
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int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
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{
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unsigned long rate;
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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moutcore = clk_get(NULL, "moutcore");
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if (IS_ERR(moutcore))
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goto err_moutcore;
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mout_mpll = clk_get(NULL, "mout_mpll");
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if (IS_ERR(mout_mpll))
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goto err_mout_mpll;
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rate = clk_get_rate(mout_mpll) / 1000;
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mout_apll = clk_get(NULL, "mout_apll");
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if (IS_ERR(mout_apll))
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goto err_mout_apll;
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info->mpll_freq_khz = rate;
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/* 800Mhz */
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info->pll_safe_idx = L2;
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info->cpu_clk = cpu_clk;
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info->volt_table = exynos4210_volt_table;
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info->freq_table = exynos4210_freq_table;
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info->set_freq = exynos4210_set_frequency;
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return 0;
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err_mout_apll:
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clk_put(mout_mpll);
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err_mout_mpll:
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clk_put(moutcore);
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err_moutcore:
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clk_put(cpu_clk);
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pr_debug("%s: failed initialization\n", __func__);
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return -EINVAL;
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}
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