39 lines
1.1 KiB
Plaintext
39 lines
1.1 KiB
Plaintext
NVIDIA Tegra20 SFLASH controller.
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Required properties:
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- compatible : should be "nvidia,tegra20-sflash".
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- reg: Should contain SFLASH registers location and length.
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- interrupts: Should contain SFLASH interrupts.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Must include the following entries:
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- spi
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- dmas : Must contain an entry for each entry in clock-names.
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See ../dma/dma.txt for details.
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- dma-names : Must include the following entries:
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- rx
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- tx
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Recommended properties:
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- spi-max-frequency: Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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Example:
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spi@7000c380 {
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compatible = "nvidia,tegra20-sflash";
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reg = <0x7000c380 0x80>;
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interrupts = <0 39 0x04>;
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spi-max-frequency = <25000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 43>;
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resets = <&tegra_car 43>;
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reset-names = "spi";
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dmas = <&apbdma 11>, <&apbdma 11>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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