175 lines
4.7 KiB
ArmAsm
175 lines
4.7 KiB
ArmAsm
/*
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* Low-level Power Management code.
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*
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* Copyright (C) 2008 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <mach/pm.h>
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#include "pm.h"
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#include "sdramc.h"
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/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
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#define PM_BASE -0x100000
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.section .bss, "wa", @nobits
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.global disable_idle_sleep
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.type disable_idle_sleep, @object
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disable_idle_sleep:
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.int 4
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.size disable_idle_sleep, . - disable_idle_sleep
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/* Keep this close to the irq handlers */
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.section .irq.text, "ax", @progbits
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/*
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* void cpu_enter_idle(void)
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*
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* Put the CPU into "idle" mode, in which it will consume
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* significantly less power.
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*
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* If an interrupt comes along in the window between
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* unmask_interrupts and the sleep instruction below, the
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* interrupt code will adjust the return address so that we
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* never execute the sleep instruction. This is required
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* because the AP7000 doesn't unmask interrupts when entering
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* sleep modes; later CPUs may not need this workaround.
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*/
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.global cpu_enter_idle
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.type cpu_enter_idle, @function
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cpu_enter_idle:
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mask_interrupts
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get_thread_info r8
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ld.w r9, r8[TI_flags]
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bld r9, TIF_NEED_RESCHED
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brcs .Lret_from_sleep
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sbr r9, TIF_CPU_GOING_TO_SLEEP
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st.w r8[TI_flags], r9
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unmask_interrupts
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sleep CPU_SLEEP_IDLE
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.size cpu_enter_idle, . - cpu_enter_idle
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/*
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* Common return path for PM functions that don't run from
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* SRAM.
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*/
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.global cpu_idle_skip_sleep
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.type cpu_idle_skip_sleep, @function
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cpu_idle_skip_sleep:
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mask_interrupts
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ld.w r9, r8[TI_flags]
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cbr r9, TIF_CPU_GOING_TO_SLEEP
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st.w r8[TI_flags], r9
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.Lret_from_sleep:
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unmask_interrupts
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retal r12
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.size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
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#ifdef CONFIG_PM
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.section .init.text, "ax", @progbits
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.global pm_exception
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.type pm_exception, @function
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pm_exception:
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/*
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* Exceptions are masked when we switch to this handler, so
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* we'll only get "unrecoverable" exceptions (offset 0.)
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*/
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sub r12, pc, . - .Lpanic_msg
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lddpc pc, .Lpanic_addr
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.align 2
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.Lpanic_addr:
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.long panic
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.Lpanic_msg:
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.asciz "Unrecoverable exception during suspend\n"
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.size pm_exception, . - pm_exception
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.global pm_irq0
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.type pm_irq0, @function
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pm_irq0:
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/* Disable interrupts and return after the sleep instruction */
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mfsr r9, SYSREG_RSR_INT0
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mtsr SYSREG_RAR_INT0, r8
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sbr r9, SYSREG_GM_OFFSET
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mtsr SYSREG_RSR_INT0, r9
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rete
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/*
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* void cpu_enter_standby(unsigned long sdramc_base)
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*
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* Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
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* are suspended and interrupts are disabled. Interrupts
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* marked as 'wakeup' event sources may still come along and
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* get us out of here.
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*
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* The SDRAM will be put into self-refresh mode (which does
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* not require a clock from the CPU), and the CPU will be put
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* into "frozen" mode (HSB bus stopped). The SDRAM controller
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* will automatically bring the SDRAM into normal mode on the
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* first access, and the power manager will automatically
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* start the HSB and CPU clocks upon a wakeup event.
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*
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* This code uses the same "skip sleep" technique as above.
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* It is very important that we jump directly to
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* cpu_after_sleep after the sleep instruction since that's
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* where we'll end up if the interrupt handler decides that we
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* need to skip the sleep instruction.
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*/
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.global pm_standby
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.type pm_standby, @function
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pm_standby:
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/*
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* interrupts are already masked at this point, and EVBA
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* points to pm_exception above.
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*/
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ld.w r10, r12[SDRAMC_LPR]
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sub r8, pc, . - 1f /* return address for irq handler */
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mov r11, SDRAMC_LPR_LPCB_SELF_RFR
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bfins r10, r11, 0, 2 /* LPCB <- self Refresh */
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sync 0 /* flush write buffer */
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st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
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ld.w r11, r12[SDRAMC_LPR]
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unmask_interrupts
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sleep CPU_SLEEP_FROZEN
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1: mask_interrupts
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retal r12
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.size pm_standby, . - pm_standby
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.global pm_suspend_to_ram
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.type pm_suspend_to_ram, @function
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pm_suspend_to_ram:
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/*
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* interrupts are already masked at this point, and EVBA
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* points to pm_exception above.
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*/
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mov r11, 0
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cache r11[2], 8 /* clean all dcache lines */
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sync 0 /* flush write buffer */
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ld.w r10, r12[SDRAMC_LPR]
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sub r8, pc, . - 1f /* return address for irq handler */
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mov r11, SDRAMC_LPR_LPCB_SELF_RFR
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bfins r10, r11, 0, 2 /* LPCB <- self refresh */
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st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
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ld.w r11, r12[SDRAMC_LPR]
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unmask_interrupts
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sleep CPU_SLEEP_STOP
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1: mask_interrupts
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retal r12
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.size pm_suspend_to_ram, . - pm_suspend_to_ram
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.global pm_sram_end
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.type pm_sram_end, @function
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pm_sram_end:
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.size pm_sram_end, 0
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#endif /* CONFIG_PM */
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