822 lines
20 KiB
C
822 lines
20 KiB
C
/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "bman_priv.h"
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#define IRQNAME "BMan portal %d"
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#define MAX_IRQNAME 16 /* big enough for "BMan portal %d" */
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/* Portal register assists */
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#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
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/* Cache-inhibited register offsets */
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#define BM_REG_RCR_PI_CINH 0x3000
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#define BM_REG_RCR_CI_CINH 0x3100
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#define BM_REG_RCR_ITR 0x3200
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#define BM_REG_CFG 0x3300
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#define BM_REG_SCN(n) (0x3400 + ((n) << 6))
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#define BM_REG_ISR 0x3e00
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#define BM_REG_IER 0x3e40
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#define BM_REG_ISDR 0x3e80
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#define BM_REG_IIR 0x3ec0
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/* Cache-enabled register offsets */
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#define BM_CL_CR 0x0000
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#define BM_CL_RR0 0x0100
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#define BM_CL_RR1 0x0140
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#define BM_CL_RCR 0x1000
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#define BM_CL_RCR_PI_CENA 0x3000
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#define BM_CL_RCR_CI_CENA 0x3100
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#else
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/* Cache-inhibited register offsets */
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#define BM_REG_RCR_PI_CINH 0x0000
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#define BM_REG_RCR_CI_CINH 0x0004
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#define BM_REG_RCR_ITR 0x0008
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#define BM_REG_CFG 0x0100
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#define BM_REG_SCN(n) (0x0200 + ((n) << 2))
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#define BM_REG_ISR 0x0e00
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#define BM_REG_IER 0x0e04
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#define BM_REG_ISDR 0x0e08
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#define BM_REG_IIR 0x0e0c
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/* Cache-enabled register offsets */
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#define BM_CL_CR 0x0000
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#define BM_CL_RR0 0x0100
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#define BM_CL_RR1 0x0140
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#define BM_CL_RCR 0x1000
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#define BM_CL_RCR_PI_CENA 0x3000
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#define BM_CL_RCR_CI_CENA 0x3100
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#endif
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/*
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* Portal modes.
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* Enum types;
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* pmode == production mode
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* cmode == consumption mode,
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* Enum values use 3 letter codes. First letter matches the portal mode,
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* remaining two letters indicate;
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* ci == cache-inhibited portal register
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* ce == cache-enabled portal register
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* vb == in-band valid-bit (cache-enabled)
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*/
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enum bm_rcr_pmode { /* matches BCSP_CFG::RPM */
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bm_rcr_pci = 0, /* PI index, cache-inhibited */
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bm_rcr_pce = 1, /* PI index, cache-enabled */
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bm_rcr_pvb = 2 /* valid-bit */
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};
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enum bm_rcr_cmode { /* s/w-only */
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bm_rcr_cci, /* CI index, cache-inhibited */
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bm_rcr_cce /* CI index, cache-enabled */
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};
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/* --- Portal structures --- */
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#define BM_RCR_SIZE 8
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/* Release Command */
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struct bm_rcr_entry {
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union {
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struct {
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u8 _ncw_verb; /* writes to this are non-coherent */
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u8 bpid; /* used with BM_RCR_VERB_CMD_BPID_SINGLE */
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u8 __reserved1[62];
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};
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struct bm_buffer bufs[8];
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};
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};
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#define BM_RCR_VERB_VBIT 0x80
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#define BM_RCR_VERB_CMD_MASK 0x70 /* one of two values; */
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#define BM_RCR_VERB_CMD_BPID_SINGLE 0x20
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#define BM_RCR_VERB_CMD_BPID_MULTI 0x30
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#define BM_RCR_VERB_BUFCOUNT_MASK 0x0f /* values 1..8 */
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struct bm_rcr {
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struct bm_rcr_entry *ring, *cursor;
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u8 ci, available, ithresh, vbit;
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#ifdef CONFIG_FSL_DPAA_CHECKING
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u32 busy;
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enum bm_rcr_pmode pmode;
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enum bm_rcr_cmode cmode;
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#endif
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};
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/* MC (Management Command) command */
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struct bm_mc_command {
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u8 _ncw_verb; /* writes to this are non-coherent */
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u8 bpid; /* used by acquire command */
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u8 __reserved[62];
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};
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#define BM_MCC_VERB_VBIT 0x80
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#define BM_MCC_VERB_CMD_MASK 0x70 /* where the verb contains; */
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#define BM_MCC_VERB_CMD_ACQUIRE 0x10
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#define BM_MCC_VERB_CMD_QUERY 0x40
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#define BM_MCC_VERB_ACQUIRE_BUFCOUNT 0x0f /* values 1..8 go here */
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/* MC result, Acquire and Query Response */
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union bm_mc_result {
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struct {
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u8 verb;
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u8 bpid;
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u8 __reserved[62];
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};
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struct bm_buffer bufs[8];
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};
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#define BM_MCR_VERB_VBIT 0x80
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#define BM_MCR_VERB_CMD_MASK BM_MCC_VERB_CMD_MASK
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#define BM_MCR_VERB_CMD_ACQUIRE BM_MCC_VERB_CMD_ACQUIRE
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#define BM_MCR_VERB_CMD_QUERY BM_MCC_VERB_CMD_QUERY
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#define BM_MCR_VERB_CMD_ERR_INVALID 0x60
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#define BM_MCR_VERB_CMD_ERR_ECC 0x70
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#define BM_MCR_VERB_ACQUIRE_BUFCOUNT BM_MCC_VERB_ACQUIRE_BUFCOUNT /* 0..8 */
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#define BM_MCR_TIMEOUT 10000 /* us */
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struct bm_mc {
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struct bm_mc_command *cr;
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union bm_mc_result *rr;
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u8 rridx, vbit;
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#ifdef CONFIG_FSL_DPAA_CHECKING
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enum {
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/* Can only be _mc_start()ed */
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mc_idle,
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/* Can only be _mc_commit()ed or _mc_abort()ed */
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mc_user,
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/* Can only be _mc_retry()ed */
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mc_hw
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} state;
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#endif
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};
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struct bm_addr {
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void *ce; /* cache-enabled */
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__be32 *ce_be; /* Same as above but for direct access */
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void __iomem *ci; /* cache-inhibited */
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};
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struct bm_portal {
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struct bm_addr addr;
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struct bm_rcr rcr;
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struct bm_mc mc;
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} ____cacheline_aligned;
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/* Cache-inhibited register access. */
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static inline u32 bm_in(struct bm_portal *p, u32 offset)
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{
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return ioread32be(p->addr.ci + offset);
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}
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static inline void bm_out(struct bm_portal *p, u32 offset, u32 val)
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{
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iowrite32be(val, p->addr.ci + offset);
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}
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/* Cache Enabled Portal Access */
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static inline void bm_cl_invalidate(struct bm_portal *p, u32 offset)
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{
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dpaa_invalidate(p->addr.ce + offset);
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}
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static inline void bm_cl_touch_ro(struct bm_portal *p, u32 offset)
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{
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dpaa_touch_ro(p->addr.ce + offset);
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}
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static inline u32 bm_ce_in(struct bm_portal *p, u32 offset)
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{
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return be32_to_cpu(*(p->addr.ce_be + (offset/4)));
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}
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struct bman_portal {
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struct bm_portal p;
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/* interrupt sources processed by portal_isr(), configurable */
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unsigned long irq_sources;
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/* probing time config params for cpu-affine portals */
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const struct bm_portal_config *config;
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char irqname[MAX_IRQNAME];
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};
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static cpumask_t affine_mask;
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static DEFINE_SPINLOCK(affine_mask_lock);
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static DEFINE_PER_CPU(struct bman_portal, bman_affine_portal);
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static inline struct bman_portal *get_affine_portal(void)
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{
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return &get_cpu_var(bman_affine_portal);
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}
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static inline void put_affine_portal(void)
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{
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put_cpu_var(bman_affine_portal);
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}
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/*
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* This object type refers to a pool, it isn't *the* pool. There may be
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* more than one such object per BMan buffer pool, eg. if different users of the
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* pool are operating via different portals.
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*/
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struct bman_pool {
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/* index of the buffer pool to encapsulate (0-63) */
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u32 bpid;
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/* Used for hash-table admin when using depletion notifications. */
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struct bman_portal *portal;
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struct bman_pool *next;
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};
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static u32 poll_portal_slow(struct bman_portal *p, u32 is);
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static irqreturn_t portal_isr(int irq, void *ptr)
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{
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struct bman_portal *p = ptr;
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struct bm_portal *portal = &p->p;
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u32 clear = p->irq_sources;
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u32 is = bm_in(portal, BM_REG_ISR) & p->irq_sources;
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if (unlikely(!is))
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return IRQ_NONE;
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clear |= poll_portal_slow(p, is);
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bm_out(portal, BM_REG_ISR, clear);
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return IRQ_HANDLED;
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}
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/* --- RCR API --- */
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#define RCR_SHIFT ilog2(sizeof(struct bm_rcr_entry))
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#define RCR_CARRY (uintptr_t)(BM_RCR_SIZE << RCR_SHIFT)
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/* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
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static struct bm_rcr_entry *rcr_carryclear(struct bm_rcr_entry *p)
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{
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uintptr_t addr = (uintptr_t)p;
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addr &= ~RCR_CARRY;
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return (struct bm_rcr_entry *)addr;
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}
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#ifdef CONFIG_FSL_DPAA_CHECKING
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/* Bit-wise logic to convert a ring pointer to a ring index */
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static int rcr_ptr2idx(struct bm_rcr_entry *e)
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{
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return ((uintptr_t)e >> RCR_SHIFT) & (BM_RCR_SIZE - 1);
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}
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#endif
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/* Increment the 'cursor' ring pointer, taking 'vbit' into account */
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static inline void rcr_inc(struct bm_rcr *rcr)
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{
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/* increment to the next RCR pointer and handle overflow and 'vbit' */
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struct bm_rcr_entry *partial = rcr->cursor + 1;
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rcr->cursor = rcr_carryclear(partial);
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if (partial != rcr->cursor)
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rcr->vbit ^= BM_RCR_VERB_VBIT;
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}
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static int bm_rcr_get_avail(struct bm_portal *portal)
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{
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struct bm_rcr *rcr = &portal->rcr;
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return rcr->available;
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}
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static int bm_rcr_get_fill(struct bm_portal *portal)
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{
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struct bm_rcr *rcr = &portal->rcr;
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return BM_RCR_SIZE - 1 - rcr->available;
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}
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static void bm_rcr_set_ithresh(struct bm_portal *portal, u8 ithresh)
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{
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struct bm_rcr *rcr = &portal->rcr;
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rcr->ithresh = ithresh;
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bm_out(portal, BM_REG_RCR_ITR, ithresh);
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}
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static void bm_rcr_cce_prefetch(struct bm_portal *portal)
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{
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__maybe_unused struct bm_rcr *rcr = &portal->rcr;
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DPAA_ASSERT(rcr->cmode == bm_rcr_cce);
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bm_cl_touch_ro(portal, BM_CL_RCR_CI_CENA);
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}
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static u8 bm_rcr_cce_update(struct bm_portal *portal)
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{
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struct bm_rcr *rcr = &portal->rcr;
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u8 diff, old_ci = rcr->ci;
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DPAA_ASSERT(rcr->cmode == bm_rcr_cce);
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rcr->ci = bm_ce_in(portal, BM_CL_RCR_CI_CENA) & (BM_RCR_SIZE - 1);
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bm_cl_invalidate(portal, BM_CL_RCR_CI_CENA);
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diff = dpaa_cyc_diff(BM_RCR_SIZE, old_ci, rcr->ci);
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rcr->available += diff;
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return diff;
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}
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static inline struct bm_rcr_entry *bm_rcr_start(struct bm_portal *portal)
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{
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struct bm_rcr *rcr = &portal->rcr;
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DPAA_ASSERT(!rcr->busy);
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if (!rcr->available)
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return NULL;
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#ifdef CONFIG_FSL_DPAA_CHECKING
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rcr->busy = 1;
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#endif
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dpaa_zero(rcr->cursor);
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return rcr->cursor;
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}
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static inline void bm_rcr_pvb_commit(struct bm_portal *portal, u8 myverb)
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{
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struct bm_rcr *rcr = &portal->rcr;
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struct bm_rcr_entry *rcursor;
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DPAA_ASSERT(rcr->busy);
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DPAA_ASSERT(rcr->pmode == bm_rcr_pvb);
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DPAA_ASSERT(rcr->available >= 1);
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dma_wmb();
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rcursor = rcr->cursor;
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rcursor->_ncw_verb = myverb | rcr->vbit;
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dpaa_flush(rcursor);
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rcr_inc(rcr);
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rcr->available--;
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#ifdef CONFIG_FSL_DPAA_CHECKING
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rcr->busy = 0;
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#endif
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}
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static int bm_rcr_init(struct bm_portal *portal, enum bm_rcr_pmode pmode,
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enum bm_rcr_cmode cmode)
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{
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struct bm_rcr *rcr = &portal->rcr;
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u32 cfg;
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u8 pi;
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rcr->ring = portal->addr.ce + BM_CL_RCR;
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rcr->ci = bm_in(portal, BM_REG_RCR_CI_CINH) & (BM_RCR_SIZE - 1);
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pi = bm_in(portal, BM_REG_RCR_PI_CINH) & (BM_RCR_SIZE - 1);
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rcr->cursor = rcr->ring + pi;
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rcr->vbit = (bm_in(portal, BM_REG_RCR_PI_CINH) & BM_RCR_SIZE) ?
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BM_RCR_VERB_VBIT : 0;
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rcr->available = BM_RCR_SIZE - 1
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- dpaa_cyc_diff(BM_RCR_SIZE, rcr->ci, pi);
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rcr->ithresh = bm_in(portal, BM_REG_RCR_ITR);
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#ifdef CONFIG_FSL_DPAA_CHECKING
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rcr->busy = 0;
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rcr->pmode = pmode;
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rcr->cmode = cmode;
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#endif
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cfg = (bm_in(portal, BM_REG_CFG) & 0xffffffe0)
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| (pmode & 0x3); /* BCSP_CFG::RPM */
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bm_out(portal, BM_REG_CFG, cfg);
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return 0;
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}
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static void bm_rcr_finish(struct bm_portal *portal)
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{
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#ifdef CONFIG_FSL_DPAA_CHECKING
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struct bm_rcr *rcr = &portal->rcr;
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int i;
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DPAA_ASSERT(!rcr->busy);
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i = bm_in(portal, BM_REG_RCR_PI_CINH) & (BM_RCR_SIZE - 1);
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if (i != rcr_ptr2idx(rcr->cursor))
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pr_crit("losing uncommitted RCR entries\n");
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i = bm_in(portal, BM_REG_RCR_CI_CINH) & (BM_RCR_SIZE - 1);
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if (i != rcr->ci)
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pr_crit("missing existing RCR completions\n");
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if (rcr->ci != rcr_ptr2idx(rcr->cursor))
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pr_crit("RCR destroyed unquiesced\n");
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#endif
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}
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/* --- Management command API --- */
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static int bm_mc_init(struct bm_portal *portal)
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{
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struct bm_mc *mc = &portal->mc;
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mc->cr = portal->addr.ce + BM_CL_CR;
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mc->rr = portal->addr.ce + BM_CL_RR0;
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mc->rridx = (mc->cr->_ncw_verb & BM_MCC_VERB_VBIT) ?
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0 : 1;
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mc->vbit = mc->rridx ? BM_MCC_VERB_VBIT : 0;
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#ifdef CONFIG_FSL_DPAA_CHECKING
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mc->state = mc_idle;
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#endif
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return 0;
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}
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static void bm_mc_finish(struct bm_portal *portal)
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{
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#ifdef CONFIG_FSL_DPAA_CHECKING
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struct bm_mc *mc = &portal->mc;
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DPAA_ASSERT(mc->state == mc_idle);
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if (mc->state != mc_idle)
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pr_crit("Losing incomplete MC command\n");
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#endif
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}
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static inline struct bm_mc_command *bm_mc_start(struct bm_portal *portal)
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{
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struct bm_mc *mc = &portal->mc;
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DPAA_ASSERT(mc->state == mc_idle);
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#ifdef CONFIG_FSL_DPAA_CHECKING
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mc->state = mc_user;
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#endif
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dpaa_zero(mc->cr);
|
|
return mc->cr;
|
|
}
|
|
|
|
static inline void bm_mc_commit(struct bm_portal *portal, u8 myverb)
|
|
{
|
|
struct bm_mc *mc = &portal->mc;
|
|
union bm_mc_result *rr = mc->rr + mc->rridx;
|
|
|
|
DPAA_ASSERT(mc->state == mc_user);
|
|
dma_wmb();
|
|
mc->cr->_ncw_verb = myverb | mc->vbit;
|
|
dpaa_flush(mc->cr);
|
|
dpaa_invalidate_touch_ro(rr);
|
|
#ifdef CONFIG_FSL_DPAA_CHECKING
|
|
mc->state = mc_hw;
|
|
#endif
|
|
}
|
|
|
|
static inline union bm_mc_result *bm_mc_result(struct bm_portal *portal)
|
|
{
|
|
struct bm_mc *mc = &portal->mc;
|
|
union bm_mc_result *rr = mc->rr + mc->rridx;
|
|
|
|
DPAA_ASSERT(mc->state == mc_hw);
|
|
/*
|
|
* The inactive response register's verb byte always returns zero until
|
|
* its command is submitted and completed. This includes the valid-bit,
|
|
* in case you were wondering...
|
|
*/
|
|
if (!rr->verb) {
|
|
dpaa_invalidate_touch_ro(rr);
|
|
return NULL;
|
|
}
|
|
mc->rridx ^= 1;
|
|
mc->vbit ^= BM_MCC_VERB_VBIT;
|
|
#ifdef CONFIG_FSL_DPAA_CHECKING
|
|
mc->state = mc_idle;
|
|
#endif
|
|
return rr;
|
|
}
|
|
|
|
static inline int bm_mc_result_timeout(struct bm_portal *portal,
|
|
union bm_mc_result **mcr)
|
|
{
|
|
int timeout = BM_MCR_TIMEOUT;
|
|
|
|
do {
|
|
*mcr = bm_mc_result(portal);
|
|
if (*mcr)
|
|
break;
|
|
udelay(1);
|
|
} while (--timeout);
|
|
|
|
return timeout;
|
|
}
|
|
|
|
/* Disable all BSCN interrupts for the portal */
|
|
static void bm_isr_bscn_disable(struct bm_portal *portal)
|
|
{
|
|
bm_out(portal, BM_REG_SCN(0), 0);
|
|
bm_out(portal, BM_REG_SCN(1), 0);
|
|
}
|
|
|
|
static int bman_create_portal(struct bman_portal *portal,
|
|
const struct bm_portal_config *c)
|
|
{
|
|
struct bm_portal *p;
|
|
int ret;
|
|
|
|
p = &portal->p;
|
|
/*
|
|
* prep the low-level portal struct with the mapped addresses from the
|
|
* config, everything that follows depends on it and "config" is more
|
|
* for (de)reference...
|
|
*/
|
|
p->addr.ce = c->addr_virt_ce;
|
|
p->addr.ce_be = c->addr_virt_ce;
|
|
p->addr.ci = c->addr_virt_ci;
|
|
if (bm_rcr_init(p, bm_rcr_pvb, bm_rcr_cce)) {
|
|
dev_err(c->dev, "RCR initialisation failed\n");
|
|
goto fail_rcr;
|
|
}
|
|
if (bm_mc_init(p)) {
|
|
dev_err(c->dev, "MC initialisation failed\n");
|
|
goto fail_mc;
|
|
}
|
|
/*
|
|
* Default to all BPIDs disabled, we enable as required at
|
|
* run-time.
|
|
*/
|
|
bm_isr_bscn_disable(p);
|
|
|
|
/* Write-to-clear any stale interrupt status bits */
|
|
bm_out(p, BM_REG_ISDR, 0xffffffff);
|
|
portal->irq_sources = 0;
|
|
bm_out(p, BM_REG_IER, 0);
|
|
bm_out(p, BM_REG_ISR, 0xffffffff);
|
|
snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
|
|
if (request_irq(c->irq, portal_isr, 0, portal->irqname, portal)) {
|
|
dev_err(c->dev, "request_irq() failed\n");
|
|
goto fail_irq;
|
|
}
|
|
if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
|
|
irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
|
|
dev_err(c->dev, "irq_set_affinity() failed\n");
|
|
goto fail_affinity;
|
|
}
|
|
|
|
/* Need RCR to be empty before continuing */
|
|
ret = bm_rcr_get_fill(p);
|
|
if (ret) {
|
|
dev_err(c->dev, "RCR unclean\n");
|
|
goto fail_rcr_empty;
|
|
}
|
|
/* Success */
|
|
portal->config = c;
|
|
|
|
bm_out(p, BM_REG_ISDR, 0);
|
|
bm_out(p, BM_REG_IIR, 0);
|
|
|
|
return 0;
|
|
|
|
fail_rcr_empty:
|
|
fail_affinity:
|
|
free_irq(c->irq, portal);
|
|
fail_irq:
|
|
bm_mc_finish(p);
|
|
fail_mc:
|
|
bm_rcr_finish(p);
|
|
fail_rcr:
|
|
return -EIO;
|
|
}
|
|
|
|
struct bman_portal *bman_create_affine_portal(const struct bm_portal_config *c)
|
|
{
|
|
struct bman_portal *portal;
|
|
int err;
|
|
|
|
portal = &per_cpu(bman_affine_portal, c->cpu);
|
|
err = bman_create_portal(portal, c);
|
|
if (err)
|
|
return NULL;
|
|
|
|
spin_lock(&affine_mask_lock);
|
|
cpumask_set_cpu(c->cpu, &affine_mask);
|
|
spin_unlock(&affine_mask_lock);
|
|
|
|
return portal;
|
|
}
|
|
|
|
static u32 poll_portal_slow(struct bman_portal *p, u32 is)
|
|
{
|
|
u32 ret = is;
|
|
|
|
if (is & BM_PIRQ_RCRI) {
|
|
bm_rcr_cce_update(&p->p);
|
|
bm_rcr_set_ithresh(&p->p, 0);
|
|
bm_out(&p->p, BM_REG_ISR, BM_PIRQ_RCRI);
|
|
is &= ~BM_PIRQ_RCRI;
|
|
}
|
|
|
|
/* There should be no status register bits left undefined */
|
|
DPAA_ASSERT(!is);
|
|
return ret;
|
|
}
|
|
|
|
int bman_p_irqsource_add(struct bman_portal *p, u32 bits)
|
|
{
|
|
unsigned long irqflags;
|
|
|
|
local_irq_save(irqflags);
|
|
p->irq_sources |= bits & BM_PIRQ_VISIBLE;
|
|
bm_out(&p->p, BM_REG_IER, p->irq_sources);
|
|
local_irq_restore(irqflags);
|
|
return 0;
|
|
}
|
|
|
|
static int bm_shutdown_pool(u32 bpid)
|
|
{
|
|
struct bm_mc_command *bm_cmd;
|
|
union bm_mc_result *bm_res;
|
|
|
|
while (1) {
|
|
struct bman_portal *p = get_affine_portal();
|
|
/* Acquire buffers until empty */
|
|
bm_cmd = bm_mc_start(&p->p);
|
|
bm_cmd->bpid = bpid;
|
|
bm_mc_commit(&p->p, BM_MCC_VERB_CMD_ACQUIRE | 1);
|
|
if (!bm_mc_result_timeout(&p->p, &bm_res)) {
|
|
put_affine_portal();
|
|
pr_crit("BMan Acquire Command timedout\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
if (!(bm_res->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT)) {
|
|
put_affine_portal();
|
|
/* Pool is empty */
|
|
return 0;
|
|
}
|
|
put_affine_portal();
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct gen_pool *bm_bpalloc;
|
|
|
|
static int bm_alloc_bpid_range(u32 *result, u32 count)
|
|
{
|
|
unsigned long addr;
|
|
|
|
addr = gen_pool_alloc(bm_bpalloc, count);
|
|
if (!addr)
|
|
return -ENOMEM;
|
|
|
|
*result = addr & ~DPAA_GENALLOC_OFF;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int bm_release_bpid(u32 bpid)
|
|
{
|
|
int ret;
|
|
|
|
ret = bm_shutdown_pool(bpid);
|
|
if (ret) {
|
|
pr_debug("BPID %d leaked\n", bpid);
|
|
return ret;
|
|
}
|
|
|
|
gen_pool_free(bm_bpalloc, bpid | DPAA_GENALLOC_OFF, 1);
|
|
return 0;
|
|
}
|
|
|
|
struct bman_pool *bman_new_pool(void)
|
|
{
|
|
struct bman_pool *pool = NULL;
|
|
u32 bpid;
|
|
|
|
if (bm_alloc_bpid_range(&bpid, 1))
|
|
return NULL;
|
|
|
|
pool = kmalloc(sizeof(*pool), GFP_KERNEL);
|
|
if (!pool)
|
|
goto err;
|
|
|
|
pool->bpid = bpid;
|
|
|
|
return pool;
|
|
err:
|
|
bm_release_bpid(bpid);
|
|
kfree(pool);
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL(bman_new_pool);
|
|
|
|
void bman_free_pool(struct bman_pool *pool)
|
|
{
|
|
bm_release_bpid(pool->bpid);
|
|
|
|
kfree(pool);
|
|
}
|
|
EXPORT_SYMBOL(bman_free_pool);
|
|
|
|
int bman_get_bpid(const struct bman_pool *pool)
|
|
{
|
|
return pool->bpid;
|
|
}
|
|
EXPORT_SYMBOL(bman_get_bpid);
|
|
|
|
static void update_rcr_ci(struct bman_portal *p, int avail)
|
|
{
|
|
if (avail)
|
|
bm_rcr_cce_prefetch(&p->p);
|
|
else
|
|
bm_rcr_cce_update(&p->p);
|
|
}
|
|
|
|
int bman_release(struct bman_pool *pool, const struct bm_buffer *bufs, u8 num)
|
|
{
|
|
struct bman_portal *p;
|
|
struct bm_rcr_entry *r;
|
|
unsigned long irqflags;
|
|
int avail, timeout = 1000; /* 1ms */
|
|
int i = num - 1;
|
|
|
|
DPAA_ASSERT(num > 0 && num <= 8);
|
|
|
|
do {
|
|
p = get_affine_portal();
|
|
local_irq_save(irqflags);
|
|
avail = bm_rcr_get_avail(&p->p);
|
|
if (avail < 2)
|
|
update_rcr_ci(p, avail);
|
|
r = bm_rcr_start(&p->p);
|
|
local_irq_restore(irqflags);
|
|
put_affine_portal();
|
|
if (likely(r))
|
|
break;
|
|
|
|
udelay(1);
|
|
} while (--timeout);
|
|
|
|
if (unlikely(!timeout))
|
|
return -ETIMEDOUT;
|
|
|
|
p = get_affine_portal();
|
|
local_irq_save(irqflags);
|
|
/*
|
|
* we can copy all but the first entry, as this can trigger badness
|
|
* with the valid-bit
|
|
*/
|
|
bm_buffer_set64(r->bufs, bm_buffer_get64(bufs));
|
|
bm_buffer_set_bpid(r->bufs, pool->bpid);
|
|
if (i)
|
|
memcpy(&r->bufs[1], &bufs[1], i * sizeof(bufs[0]));
|
|
|
|
bm_rcr_pvb_commit(&p->p, BM_RCR_VERB_CMD_BPID_SINGLE |
|
|
(num & BM_RCR_VERB_BUFCOUNT_MASK));
|
|
|
|
local_irq_restore(irqflags);
|
|
put_affine_portal();
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(bman_release);
|
|
|
|
int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num)
|
|
{
|
|
struct bman_portal *p = get_affine_portal();
|
|
struct bm_mc_command *mcc;
|
|
union bm_mc_result *mcr;
|
|
int ret;
|
|
|
|
DPAA_ASSERT(num > 0 && num <= 8);
|
|
|
|
mcc = bm_mc_start(&p->p);
|
|
mcc->bpid = pool->bpid;
|
|
bm_mc_commit(&p->p, BM_MCC_VERB_CMD_ACQUIRE |
|
|
(num & BM_MCC_VERB_ACQUIRE_BUFCOUNT));
|
|
if (!bm_mc_result_timeout(&p->p, &mcr)) {
|
|
put_affine_portal();
|
|
pr_crit("BMan Acquire Timeout\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
ret = mcr->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT;
|
|
if (bufs)
|
|
memcpy(&bufs[0], &mcr->bufs[0], num * sizeof(bufs[0]));
|
|
|
|
put_affine_portal();
|
|
if (ret != num)
|
|
ret = -ENOMEM;
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL(bman_acquire);
|
|
|
|
const struct bm_portal_config *
|
|
bman_get_bm_portal_config(const struct bman_portal *portal)
|
|
{
|
|
return portal->config;
|
|
}
|