437 lines
11 KiB
C
437 lines
11 KiB
C
/*
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* Broadcom specific AMBA
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* Broadcom MIPS32 74K core driver
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*
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* Copyright 2009, Broadcom Corporation
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* Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
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* Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com>
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* Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/serial_reg.h>
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#include <linux/time.h>
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enum bcma_boot_dev {
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BCMA_BOOT_DEV_UNK = 0,
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BCMA_BOOT_DEV_ROM,
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BCMA_BOOT_DEV_PARALLEL,
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BCMA_BOOT_DEV_SERIAL,
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BCMA_BOOT_DEV_NAND,
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};
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static const char * const part_probes[] = { "bcm47xxpart", NULL };
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static struct physmap_flash_data bcma_pflash_data = {
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.part_probe_types = part_probes,
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};
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static struct resource bcma_pflash_resource = {
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.name = "bcma_pflash",
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.flags = IORESOURCE_MEM,
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};
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struct platform_device bcma_pflash_dev = {
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.name = "physmap-flash",
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.dev = {
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.platform_data = &bcma_pflash_data,
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},
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.resource = &bcma_pflash_resource,
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.num_resources = 1,
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};
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/* The 47162a0 hangs when reading MIPS DMP registers registers */
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static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
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{
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return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 &&
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dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K;
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}
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/* The 5357b0 hangs when reading USB20H DMP registers */
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static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
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{
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return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
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dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) &&
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dev->bus->chipinfo.pkg == 11 &&
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dev->id.id == BCMA_CORE_USB20_HOST;
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}
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static inline u32 mips_read32(struct bcma_drv_mips *mcore,
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u16 offset)
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{
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return bcma_read32(mcore->core, offset);
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}
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static inline void mips_write32(struct bcma_drv_mips *mcore,
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u16 offset,
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u32 value)
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{
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bcma_write32(mcore->core, offset, value);
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}
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static const u32 ipsflag_irq_mask[] = {
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0,
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BCMA_MIPS_IPSFLAG_IRQ1,
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BCMA_MIPS_IPSFLAG_IRQ2,
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BCMA_MIPS_IPSFLAG_IRQ3,
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BCMA_MIPS_IPSFLAG_IRQ4,
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};
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static const u32 ipsflag_irq_shift[] = {
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0,
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BCMA_MIPS_IPSFLAG_IRQ1_SHIFT,
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BCMA_MIPS_IPSFLAG_IRQ2_SHIFT,
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BCMA_MIPS_IPSFLAG_IRQ3_SHIFT,
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BCMA_MIPS_IPSFLAG_IRQ4_SHIFT,
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};
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static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
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{
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u32 flag;
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if (bcma_core_mips_bcm47162a0_quirk(dev))
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return dev->core_index;
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if (bcma_core_mips_bcm5357b0_quirk(dev))
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return dev->core_index;
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flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
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if (flag)
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return flag & 0x1F;
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else
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return 0x3f;
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}
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/* Get the MIPS IRQ assignment for a specified device.
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* If unassigned, 0 is returned.
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* If disabled, 5 is returned.
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* If not supported, 6 is returned.
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*/
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static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
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{
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struct bcma_device *mdev = dev->bus->drv_mips.core;
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u32 irqflag;
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unsigned int irq;
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irqflag = bcma_core_mips_irqflag(dev);
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if (irqflag == 0x3f)
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return 6;
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for (irq = 0; irq <= 4; irq++)
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if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
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(1 << irqflag))
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return irq;
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return 5;
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}
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unsigned int bcma_core_irq(struct bcma_device *dev)
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{
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unsigned int mips_irq = bcma_core_mips_irq(dev);
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return mips_irq <= 4 ? mips_irq + 2 : 0;
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}
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EXPORT_SYMBOL(bcma_core_irq);
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static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
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{
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unsigned int oldirq = bcma_core_mips_irq(dev);
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struct bcma_bus *bus = dev->bus;
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struct bcma_device *mdev = bus->drv_mips.core;
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u32 irqflag;
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irqflag = bcma_core_mips_irqflag(dev);
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BUG_ON(oldirq == 6);
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dev->irq = irq + 2;
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/* clear the old irq */
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if (oldirq == 0)
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bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
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bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
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~(1 << irqflag));
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else if (oldirq != 5)
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bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
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/* assign the new one */
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if (irq == 0) {
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bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
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bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
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(1 << irqflag));
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} else {
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u32 irqinitmask = bcma_read32(mdev,
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BCMA_MIPS_MIPS74K_INTMASK(irq));
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if (irqinitmask) {
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struct bcma_device *core;
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/* backplane irq line is in use, find out who uses
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* it and set user to irq 0
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*/
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list_for_each_entry(core, &bus->cores, list) {
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if ((1 << bcma_core_mips_irqflag(core)) ==
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irqinitmask) {
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bcma_core_mips_set_irq(core, 0);
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break;
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}
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}
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}
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bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
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1 << irqflag);
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}
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bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
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dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
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}
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static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
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u16 coreid, u8 unit)
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{
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struct bcma_device *core;
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core = bcma_find_core_unit(bus, coreid, unit);
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if (!core) {
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bcma_warn(bus,
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"Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
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coreid, unit);
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return;
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}
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bcma_core_mips_set_irq(core, irq);
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}
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static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
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{
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int i;
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static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
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printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
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for (i = 0; i <= 6; i++)
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printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
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printk("\n");
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}
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static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
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{
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struct bcma_device *core;
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list_for_each_entry(core, &bus->cores, list) {
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bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
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}
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}
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u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
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{
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struct bcma_bus *bus = mcore->core->bus;
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if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
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return bcma_pmu_get_cpu_clock(&bus->drv_cc);
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bcma_err(bus, "No PMU available, need this to get the cpu clock\n");
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return 0;
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}
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EXPORT_SYMBOL(bcma_cpu_clock);
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static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
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{
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struct bcma_drv_cc *cc = &bus->drv_cc;
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u8 cc_rev = cc->core->id.rev;
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if (cc_rev == 42) {
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struct bcma_device *core;
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core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
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if (core) {
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switch (bcma_aread32(core, BCMA_IOST) &
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BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
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case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
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return BCMA_BOOT_DEV_SERIAL;
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case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
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return BCMA_BOOT_DEV_NAND;
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case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
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default:
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return BCMA_BOOT_DEV_ROM;
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}
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}
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} else {
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if (cc_rev == 38) {
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if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
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return BCMA_BOOT_DEV_NAND;
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else if (cc->status & BIT(5))
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return BCMA_BOOT_DEV_ROM;
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}
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if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
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BCMA_CC_FLASHT_PARA)
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return BCMA_BOOT_DEV_PARALLEL;
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else
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return BCMA_BOOT_DEV_SERIAL;
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}
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return BCMA_BOOT_DEV_SERIAL;
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}
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static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
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{
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struct bcma_bus *bus = mcore->core->bus;
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struct bcma_drv_cc *cc = &bus->drv_cc;
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struct bcma_pflash *pflash = &cc->pflash;
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enum bcma_boot_dev boot_dev;
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switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
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case BCMA_CC_FLASHT_STSER:
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case BCMA_CC_FLASHT_ATSER:
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bcma_debug(bus, "Found serial flash\n");
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bcma_sflash_init(cc);
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break;
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case BCMA_CC_FLASHT_PARA:
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bcma_debug(bus, "Found parallel flash\n");
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pflash->present = true;
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pflash->window = BCMA_SOC_FLASH2;
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pflash->window_size = BCMA_SOC_FLASH2_SZ;
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if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
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BCMA_CC_FLASH_CFG_DS) == 0)
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pflash->buswidth = 1;
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else
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pflash->buswidth = 2;
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bcma_pflash_data.width = pflash->buswidth;
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bcma_pflash_resource.start = pflash->window;
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bcma_pflash_resource.end = pflash->window + pflash->window_size;
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break;
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default:
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bcma_err(bus, "Flash type not supported\n");
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}
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if (cc->core->id.rev == 38 ||
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bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
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if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
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bcma_debug(bus, "Found NAND flash\n");
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bcma_nflash_init(cc);
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}
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}
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/* Determine flash type this SoC boots from */
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boot_dev = bcma_boot_dev(bus);
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switch (boot_dev) {
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case BCMA_BOOT_DEV_PARALLEL:
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case BCMA_BOOT_DEV_SERIAL:
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/* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
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break;
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case BCMA_BOOT_DEV_NAND:
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/* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
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break;
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default:
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break;
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}
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}
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void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
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{
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struct bcma_bus *bus = mcore->core->bus;
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if (mcore->early_setup_done)
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return;
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bcma_chipco_serial_init(&bus->drv_cc);
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bcma_core_mips_flash_detect(mcore);
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mcore->early_setup_done = true;
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}
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static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
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{
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struct bcma_device *cpu, *pcie, *i2s;
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/* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
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* (IRQ flags > 7 are ignored when setting the interrupt masks)
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*/
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if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
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bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
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return;
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cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
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pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
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i2s = bcma_find_core(bus, BCMA_CORE_I2S);
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if (cpu && pcie && i2s &&
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bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
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bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
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bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
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bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
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bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
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bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
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bcma_debug(bus,
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"Moved i2s interrupt to oob line 7 instead of 8\n");
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}
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}
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void bcma_core_mips_init(struct bcma_drv_mips *mcore)
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{
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struct bcma_bus *bus;
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struct bcma_device *core;
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bus = mcore->core->bus;
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if (mcore->setup_done)
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return;
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bcma_debug(bus, "Initializing MIPS core...\n");
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bcma_core_mips_early_init(mcore);
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bcma_fix_i2s_irqflag(bus);
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switch (bus->chipinfo.id) {
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case BCMA_CHIP_ID_BCM4716:
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case BCMA_CHIP_ID_BCM4748:
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bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
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bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
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bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
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bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
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bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
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bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
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break;
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case BCMA_CHIP_ID_BCM5356:
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case BCMA_CHIP_ID_BCM47162:
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case BCMA_CHIP_ID_BCM53572:
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bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
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bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
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bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
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break;
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case BCMA_CHIP_ID_BCM5357:
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case BCMA_CHIP_ID_BCM4749:
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bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
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bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
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bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
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bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
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bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
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break;
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case BCMA_CHIP_ID_BCM4706:
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bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
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bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
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0);
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bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
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bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
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bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
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0);
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break;
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default:
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list_for_each_entry(core, &bus->cores, list) {
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core->irq = bcma_core_irq(core);
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}
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bcma_err(bus,
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"Unknown device (0x%x) found, can not configure IRQs\n",
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bus->chipinfo.id);
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}
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bcma_debug(bus, "IRQ reconfiguration done\n");
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bcma_core_mips_dump_irq(bus);
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mcore->setup_done = true;
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}
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