146 lines
4.3 KiB
C
146 lines
4.3 KiB
C
/* $Id: mmu_context.h,v 1.54 2002/02/09 19:49:31 davem Exp $ */
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#ifndef __SPARC64_MMU_CONTEXT_H
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#define __SPARC64_MMU_CONTEXT_H
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/* Derived heavily from Linus's Alpha/AXP ASN code... */
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#ifndef __ASSEMBLY__
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#include <linux/spinlock.h>
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#include <asm/system.h>
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#include <asm/spitfire.h>
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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extern spinlock_t ctx_alloc_lock;
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extern unsigned long tlb_context_cache;
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extern unsigned long mmu_context_bmap[];
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extern void get_new_mmu_context(struct mm_struct *mm);
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/* Initialize a new mmu context. This is invoked when a new
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* address space instance (unique or shared) is instantiated.
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* This just needs to set mm->context to an invalid context.
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*/
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#define init_new_context(__tsk, __mm) \
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(((__mm)->context.sparc64_ctx_val = 0UL), 0)
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/* Destroy a dead context. This occurs when mmput drops the
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* mm_users count to zero, the mmaps have been released, and
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* all the page tables have been flushed. Our job is to destroy
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* any remaining processor-specific state, and in the sparc64
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* case this just means freeing up the mmu context ID held by
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* this task if valid.
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*/
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#define destroy_context(__mm) \
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do { spin_lock(&ctx_alloc_lock); \
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if (CTX_VALID((__mm)->context)) { \
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unsigned long nr = CTX_NRBITS((__mm)->context); \
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mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); \
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} \
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spin_unlock(&ctx_alloc_lock); \
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} while(0)
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/* Reload the two core values used by TLB miss handler
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* processing on sparc64. They are:
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* 1) The physical address of mm->pgd, when full page
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* table walks are necessary, this is where the
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* search begins.
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* 2) A "PGD cache". For 32-bit tasks only pgd[0] is
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* ever used since that maps the entire low 4GB
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* completely. To speed up TLB miss processing we
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* make this value available to the handlers. This
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* decreases the amount of memory traffic incurred.
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*/
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#define reload_tlbmiss_state(__tsk, __mm) \
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do { \
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register unsigned long paddr asm("o5"); \
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register unsigned long pgd_cache asm("o4"); \
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paddr = __pa((__mm)->pgd); \
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pgd_cache = 0UL; \
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if ((__tsk)->thread_info->flags & _TIF_32BIT) \
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pgd_cache = get_pgd_cache((__mm)->pgd); \
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__asm__ __volatile__("wrpr %%g0, 0x494, %%pstate\n\t" \
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"mov %3, %%g4\n\t" \
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"mov %0, %%g7\n\t" \
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"stxa %1, [%%g4] %2\n\t" \
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"membar #Sync\n\t" \
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"wrpr %%g0, 0x096, %%pstate" \
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: /* no outputs */ \
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: "r" (paddr), "r" (pgd_cache),\
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"i" (ASI_DMMU), "i" (TSB_REG)); \
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} while(0)
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/* Set MMU context in the actual hardware. */
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#define load_secondary_context(__mm) \
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__asm__ __volatile__("stxa %0, [%1] %2\n\t" \
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"flush %%g6" \
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: /* No outputs */ \
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: "r" (CTX_HWBITS((__mm)->context)), \
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"r" (SECONDARY_CONTEXT), "i" (ASI_DMMU))
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extern void __flush_tlb_mm(unsigned long, unsigned long);
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/* Switch the current MM context. */
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static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk)
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{
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unsigned long ctx_valid;
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spin_lock(&mm->page_table_lock);
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if (CTX_VALID(mm->context))
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ctx_valid = 1;
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else
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ctx_valid = 0;
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if (!ctx_valid || (old_mm != mm)) {
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if (!ctx_valid)
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get_new_mmu_context(mm);
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load_secondary_context(mm);
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reload_tlbmiss_state(tsk, mm);
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}
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{
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int cpu = smp_processor_id();
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/* Even if (mm == old_mm) we _must_ check
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* the cpu_vm_mask. If we do not we could
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* corrupt the TLB state because of how
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* smp_flush_tlb_{page,range,mm} on sparc64
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* and lazy tlb switches work. -DaveM
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*/
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if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) {
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cpu_set(cpu, mm->cpu_vm_mask);
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__flush_tlb_mm(CTX_HWBITS(mm->context),
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SECONDARY_CONTEXT);
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}
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}
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spin_unlock(&mm->page_table_lock);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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/* Activate a new MM instance for the current task. */
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static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
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{
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int cpu;
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spin_lock(&mm->page_table_lock);
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if (!CTX_VALID(mm->context))
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get_new_mmu_context(mm);
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cpu = smp_processor_id();
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if (!cpu_isset(cpu, mm->cpu_vm_mask))
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cpu_set(cpu, mm->cpu_vm_mask);
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spin_unlock(&mm->page_table_lock);
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load_secondary_context(mm);
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__flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT);
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reload_tlbmiss_state(current, mm);
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}
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__SPARC64_MMU_CONTEXT_H) */
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