420 lines
10 KiB
C
420 lines
10 KiB
C
/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Copyright (c) 2013 Linaro Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file contains the utility functions to register the pll clocks.
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*/
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#include <linux/errno.h>
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#include "clk.h"
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#include "clk-pll.h"
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/*
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* PLL35xx Clock Type
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*/
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#define PLL35XX_MDIV_MASK (0x3FF)
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#define PLL35XX_PDIV_MASK (0x3F)
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#define PLL35XX_SDIV_MASK (0x7)
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#define PLL35XX_MDIV_SHIFT (16)
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#define PLL35XX_PDIV_SHIFT (8)
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#define PLL35XX_SDIV_SHIFT (0)
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struct samsung_clk_pll35xx {
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struct clk_hw hw;
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const void __iomem *con_reg;
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};
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#define to_clk_pll35xx(_hw) container_of(_hw, struct samsung_clk_pll35xx, hw)
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static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct samsung_clk_pll35xx *pll = to_clk_pll35xx(hw);
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u32 mdiv, pdiv, sdiv, pll_con;
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u64 fvco = parent_rate;
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pll_con = __raw_readl(pll->con_reg);
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mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
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pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
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sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
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fvco *= mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned long)fvco;
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}
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static const struct clk_ops samsung_pll35xx_clk_ops = {
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.recalc_rate = samsung_pll35xx_recalc_rate,
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};
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struct clk * __init samsung_clk_register_pll35xx(const char *name,
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const char *pname, const void __iomem *con_reg)
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{
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struct samsung_clk_pll35xx *pll;
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struct clk *clk;
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struct clk_init_data init;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll) {
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pr_err("%s: could not allocate pll clk %s\n", __func__, name);
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return NULL;
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}
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init.name = name;
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init.ops = &samsung_pll35xx_clk_ops;
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init.flags = CLK_GET_RATE_NOCACHE;
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init.parent_names = &pname;
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init.num_parents = 1;
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pll->hw.init = &init;
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pll->con_reg = con_reg;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register pll clock %s\n", __func__,
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name);
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kfree(pll);
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}
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if (clk_register_clkdev(clk, name, NULL))
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pr_err("%s: failed to register lookup for %s", __func__, name);
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return clk;
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}
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/*
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* PLL36xx Clock Type
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*/
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#define PLL36XX_KDIV_MASK (0xFFFF)
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#define PLL36XX_MDIV_MASK (0x1FF)
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#define PLL36XX_PDIV_MASK (0x3F)
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#define PLL36XX_SDIV_MASK (0x7)
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#define PLL36XX_MDIV_SHIFT (16)
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#define PLL36XX_PDIV_SHIFT (8)
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#define PLL36XX_SDIV_SHIFT (0)
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struct samsung_clk_pll36xx {
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struct clk_hw hw;
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const void __iomem *con_reg;
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};
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#define to_clk_pll36xx(_hw) container_of(_hw, struct samsung_clk_pll36xx, hw)
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static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct samsung_clk_pll36xx *pll = to_clk_pll36xx(hw);
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u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
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u64 fvco = parent_rate;
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pll_con0 = __raw_readl(pll->con_reg);
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pll_con1 = __raw_readl(pll->con_reg + 4);
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mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
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pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
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sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
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kdiv = pll_con1 & PLL36XX_KDIV_MASK;
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fvco *= (mdiv << 16) + kdiv;
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do_div(fvco, (pdiv << sdiv));
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fvco >>= 16;
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return (unsigned long)fvco;
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}
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static const struct clk_ops samsung_pll36xx_clk_ops = {
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.recalc_rate = samsung_pll36xx_recalc_rate,
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};
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struct clk * __init samsung_clk_register_pll36xx(const char *name,
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const char *pname, const void __iomem *con_reg)
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{
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struct samsung_clk_pll36xx *pll;
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struct clk *clk;
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struct clk_init_data init;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll) {
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pr_err("%s: could not allocate pll clk %s\n", __func__, name);
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return NULL;
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}
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init.name = name;
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init.ops = &samsung_pll36xx_clk_ops;
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init.flags = CLK_GET_RATE_NOCACHE;
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init.parent_names = &pname;
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init.num_parents = 1;
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pll->hw.init = &init;
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pll->con_reg = con_reg;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register pll clock %s\n", __func__,
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name);
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kfree(pll);
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}
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if (clk_register_clkdev(clk, name, NULL))
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pr_err("%s: failed to register lookup for %s", __func__, name);
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return clk;
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}
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/*
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* PLL45xx Clock Type
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*/
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#define PLL45XX_MDIV_MASK (0x3FF)
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#define PLL45XX_PDIV_MASK (0x3F)
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#define PLL45XX_SDIV_MASK (0x7)
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#define PLL45XX_MDIV_SHIFT (16)
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#define PLL45XX_PDIV_SHIFT (8)
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#define PLL45XX_SDIV_SHIFT (0)
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struct samsung_clk_pll45xx {
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struct clk_hw hw;
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enum pll45xx_type type;
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const void __iomem *con_reg;
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};
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#define to_clk_pll45xx(_hw) container_of(_hw, struct samsung_clk_pll45xx, hw)
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static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct samsung_clk_pll45xx *pll = to_clk_pll45xx(hw);
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u32 mdiv, pdiv, sdiv, pll_con;
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u64 fvco = parent_rate;
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pll_con = __raw_readl(pll->con_reg);
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mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
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pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
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sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
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if (pll->type == pll_4508)
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sdiv = sdiv - 1;
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fvco *= mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned long)fvco;
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}
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static const struct clk_ops samsung_pll45xx_clk_ops = {
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.recalc_rate = samsung_pll45xx_recalc_rate,
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};
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struct clk * __init samsung_clk_register_pll45xx(const char *name,
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const char *pname, const void __iomem *con_reg,
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enum pll45xx_type type)
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{
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struct samsung_clk_pll45xx *pll;
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struct clk *clk;
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struct clk_init_data init;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll) {
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pr_err("%s: could not allocate pll clk %s\n", __func__, name);
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return NULL;
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}
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init.name = name;
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init.ops = &samsung_pll45xx_clk_ops;
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init.flags = CLK_GET_RATE_NOCACHE;
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init.parent_names = &pname;
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init.num_parents = 1;
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pll->hw.init = &init;
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pll->con_reg = con_reg;
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pll->type = type;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register pll clock %s\n", __func__,
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name);
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kfree(pll);
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}
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if (clk_register_clkdev(clk, name, NULL))
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pr_err("%s: failed to register lookup for %s", __func__, name);
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return clk;
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}
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/*
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* PLL46xx Clock Type
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*/
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#define PLL46XX_MDIV_MASK (0x1FF)
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#define PLL46XX_PDIV_MASK (0x3F)
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#define PLL46XX_SDIV_MASK (0x7)
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#define PLL46XX_MDIV_SHIFT (16)
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#define PLL46XX_PDIV_SHIFT (8)
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#define PLL46XX_SDIV_SHIFT (0)
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#define PLL46XX_KDIV_MASK (0xFFFF)
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#define PLL4650C_KDIV_MASK (0xFFF)
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#define PLL46XX_KDIV_SHIFT (0)
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struct samsung_clk_pll46xx {
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struct clk_hw hw;
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enum pll46xx_type type;
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const void __iomem *con_reg;
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};
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#define to_clk_pll46xx(_hw) container_of(_hw, struct samsung_clk_pll46xx, hw)
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static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct samsung_clk_pll46xx *pll = to_clk_pll46xx(hw);
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u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
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u64 fvco = parent_rate;
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pll_con0 = __raw_readl(pll->con_reg);
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pll_con1 = __raw_readl(pll->con_reg + 4);
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mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
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pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
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sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
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kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
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pll_con1 & PLL46XX_KDIV_MASK;
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shift = pll->type == pll_4600 ? 16 : 10;
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fvco *= (mdiv << shift) + kdiv;
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do_div(fvco, (pdiv << sdiv));
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fvco >>= shift;
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return (unsigned long)fvco;
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}
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static const struct clk_ops samsung_pll46xx_clk_ops = {
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.recalc_rate = samsung_pll46xx_recalc_rate,
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};
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struct clk * __init samsung_clk_register_pll46xx(const char *name,
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const char *pname, const void __iomem *con_reg,
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enum pll46xx_type type)
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{
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struct samsung_clk_pll46xx *pll;
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struct clk *clk;
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struct clk_init_data init;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll) {
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pr_err("%s: could not allocate pll clk %s\n", __func__, name);
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return NULL;
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}
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init.name = name;
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init.ops = &samsung_pll46xx_clk_ops;
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init.flags = CLK_GET_RATE_NOCACHE;
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init.parent_names = &pname;
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init.num_parents = 1;
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pll->hw.init = &init;
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pll->con_reg = con_reg;
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pll->type = type;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register pll clock %s\n", __func__,
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name);
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kfree(pll);
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}
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if (clk_register_clkdev(clk, name, NULL))
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pr_err("%s: failed to register lookup for %s", __func__, name);
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return clk;
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}
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/*
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* PLL2550x Clock Type
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*/
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#define PLL2550X_R_MASK (0x1)
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#define PLL2550X_P_MASK (0x3F)
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#define PLL2550X_M_MASK (0x3FF)
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#define PLL2550X_S_MASK (0x7)
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#define PLL2550X_R_SHIFT (20)
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#define PLL2550X_P_SHIFT (14)
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#define PLL2550X_M_SHIFT (4)
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#define PLL2550X_S_SHIFT (0)
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struct samsung_clk_pll2550x {
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struct clk_hw hw;
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const void __iomem *reg_base;
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unsigned long offset;
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};
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#define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw)
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static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
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u32 r, p, m, s, pll_stat;
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u64 fvco = parent_rate;
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pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
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r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
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if (!r)
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return 0;
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p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
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m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
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s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
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fvco *= m;
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do_div(fvco, (p << s));
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return (unsigned long)fvco;
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}
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static const struct clk_ops samsung_pll2550x_clk_ops = {
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.recalc_rate = samsung_pll2550x_recalc_rate,
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};
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struct clk * __init samsung_clk_register_pll2550x(const char *name,
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const char *pname, const void __iomem *reg_base,
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const unsigned long offset)
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{
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struct samsung_clk_pll2550x *pll;
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struct clk *clk;
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struct clk_init_data init;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll) {
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pr_err("%s: could not allocate pll clk %s\n", __func__, name);
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return NULL;
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}
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init.name = name;
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init.ops = &samsung_pll2550x_clk_ops;
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init.flags = CLK_GET_RATE_NOCACHE;
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init.parent_names = &pname;
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init.num_parents = 1;
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pll->hw.init = &init;
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pll->reg_base = reg_base;
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pll->offset = offset;
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clk = clk_register(NULL, &pll->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register pll clock %s\n", __func__,
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name);
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kfree(pll);
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}
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if (clk_register_clkdev(clk, name, NULL))
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pr_err("%s: failed to register lookup for %s", __func__, name);
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return clk;
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}
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