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linux_old1/arch/arm/boot/dts/omap4.dtsi

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/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
#include "skeleton.dtsi"
/ {
compatible = "ti,omap4430", "ti,omap4";
interrupt-parent = <&gic>;
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&L2>;
reg = <0x0>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&L2>;
reg = <0x1>;
};
};
gic: interrupt-controller@48241000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48241000 0x1000>,
<0x48240100 0x0100>;
};
L2: l2-cache-controller@48242000 {
compatible = "arm,pl310-cache";
reg = <0x48242000 0x1000>;
cache-unified;
cache-level = <2>;
};
local-timer@48240600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x48240600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
};
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
};
dsp {
compatible = "ti,omap3-c64";
ti,hwmods = "dsp";
};
iva {
compatible = "ti,ivahd";
ti,hwmods = "iva";
};
};
/*
* XXX: Use a flat representation of the OMAP4 interconnect.
* The real OMAP interconnect network is quite complex.
* Since that will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "ti,omap4-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
reg = <0x44000000 0x1000>,
<0x44800000 0x2000>,
<0x45000000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
cm1: cm1@4a004000 {
compatible = "ti,omap4-cm1";
reg = <0x4a004000 0x2000>;
cm1_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm1_clockdomains: clockdomains {
};
};
prm: prm@4a306000 {
compatible = "ti,omap4-prm";
reg = <0x4a306000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
cm2: cm2@4a008000 {
compatible = "ti,omap4-cm2";
reg = <0x4a008000 0x3000>;
cm2_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm2_clockdomains: clockdomains {
};
};
scrm: scrm@4a30a000 {
compatible = "ti,omap4-scrm";
reg = <0x4a30a000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@4a304000 {
compatible = "ti,omap-counter32k";
reg = <0x4a304000 0x20>;
ti,hwmods = "counter_32k";
};
omap4_pmx_core: pinmux@4a100040 {
compatible = "ti,omap4-padconf", "pinctrl-single";
reg = <0x4a100040 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap4_pmx_wkup: pinmux@4a31e040 {
compatible = "ti,omap4-padconf", "pinctrl-single";
reg = <0x4a31e040 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
};
gpio1: gpio@4a310000 {
compatible = "ti,omap4-gpio";
reg = <0x4a310000 0x200>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio1";
ti,gpio-always-on;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@48055000 {
compatible = "ti,omap4-gpio";
reg = <0x48055000 0x200>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@48057000 {
compatible = "ti,omap4-gpio";
reg = <0x48057000 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@48059000 {
compatible = "ti,omap4-gpio";
reg = <0x48059000 0x200>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@4805b000 {
compatible = "ti,omap4-gpio";
reg = <0x4805b000 0x200>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@4805d000 {
compatible = "ti,omap4-gpio";
reg = <0x4805d000 0x200>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
ti,no-idle-on-init;
};
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
reg = <0x4806a000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
};
uart2: serial@4806c000 {
compatible = "ti,omap4-uart";
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
};
uart3: serial@48020000 {
compatible = "ti,omap4-uart";
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
};
uart4: serial@4806e000 {
compatible = "ti,omap4-uart";
reg = <0x4806e000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
};
hwspinlock: spinlock@4a0f6000 {
compatible = "ti,omap4-hwspinlock";
reg = <0x4a0f6000 0x1000>;
ti,hwmods = "spinlock";
};
i2c1: i2c@48070000 {
compatible = "ti,omap4-i2c";
reg = <0x48070000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
};
i2c2: i2c@48072000 {
compatible = "ti,omap4-i2c";
reg = <0x48072000 0x100>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
};
i2c3: i2c@48060000 {
compatible = "ti,omap4-i2c";
reg = <0x48060000 0x100>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
};
i2c4: i2c@48350000 {
compatible = "ti,omap4-i2c";
reg = <0x48350000 0x100>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c4";
};
mcspi1: spi@48098000 {
compatible = "ti,omap4-mcspi";
reg = <0x48098000 0x200>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
<&sdma 37>,
<&sdma 38>,
<&sdma 39>,
<&sdma 40>,
<&sdma 41>,
<&sdma 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
};
mcspi2: spi@4809a000 {
compatible = "ti,omap4-mcspi";
reg = <0x4809a000 0x200>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
<&sdma 45>,
<&sdma 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
mcspi3: spi@480b8000 {
compatible = "ti,omap4-mcspi";
reg = <0x480b8000 0x200>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>, <&sdma 16>;
dma-names = "tx0", "rx0";
};
mcspi4: spi@480ba000 {
compatible = "ti,omap4-mcspi";
reg = <0x480ba000 0x200>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
};
mmc1: mmc@4809c000 {
compatible = "ti,omap4-hsmmc";
reg = <0x4809c000 0x400>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
};
mmc2: mmc@480b4000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
};
mmc3: mmc@480ad000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480ad000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
};
mmc4: mmc@480d1000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480d1000 0x400>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
dmas = <&sdma 57>, <&sdma 58>;
dma-names = "tx", "rx";
};
mmc5: mmc@480d5000 {
compatible = "ti,omap4-hsmmc";
reg = <0x480d5000 0x400>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc5";
ti,needs-special-reset;
dmas = <&sdma 59>, <&sdma 60>;
dma-names = "tx", "rx";
};
wdt2: wdt@4a314000 {
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
reg = <0x4a314000 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "wd_timer2";
};
mcpdm: mcpdm@40132000 {
compatible = "ti,omap4-mcpdm";
reg = <0x40132000 0x7f>, /* MPU private access */
<0x49032000 0x7f>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mcpdm";
dmas = <&sdma 65>,
<&sdma 66>;
dma-names = "up_link", "dn_link";
};
dmic: dmic@4012e000 {
compatible = "ti,omap4-dmic";
reg = <0x4012e000 0x7f>, /* MPU private access */
<0x4902e000 0x7f>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dmic";
dmas = <&sdma 67>;
dma-names = "up_link";
};
mcbsp1: mcbsp@40122000 {
compatible = "ti,omap4-mcbsp";
reg = <0x40122000 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
};
mcbsp2: mcbsp@40124000 {
compatible = "ti,omap4-mcbsp";
reg = <0x40124000 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp2";
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
};
mcbsp3: mcbsp@40126000 {
compatible = "ti,omap4-mcbsp";
reg = <0x40126000 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3";
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
};
mcbsp4: mcbsp@48096000 {
compatible = "ti,omap4-mcbsp";
reg = <0x48096000 0xff>; /* L4 Interconnect */
reg-names = "mpu";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp4";
dmas = <&sdma 31>,
<&sdma 32>;
dma-names = "tx", "rx";
};
keypad: keypad@4a31c000 {
compatible = "ti,omap4-keypad";
reg = <0x4a31c000 0x80>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
reg-names = "mpu";
ti,hwmods = "kbd";
};
emif1: emif@4c000000 {
compatible = "ti,emif-4d";
reg = <0x4c000000 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "emif1";
ti,no-idle-on-init;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
emif2: emif@4d000000 {
compatible = "ti,emif-4d";
reg = <0x4d000000 0x100>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "emif2";
ti,no-idle-on-init;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
ocp2scp@4a0ad000 {
compatible = "ti,omap-ocp2scp";
reg = <0x4a0ad000 0x1f>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp_usb_phy";
usb2_phy: usb2phy@4a0ad080 {
compatible = "ti,omap-usb2";
reg = <0x4a0ad080 0x58>;
ctrl-module = <&omap_control_usb2phy>;
#phy-cells = <0>;
};
};
timer1: timer@4a318000 {
compatible = "ti,omap3430-timer";
reg = <0x4a318000 0x80>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
};
timer2: timer@48032000 {
compatible = "ti,omap3430-timer";
reg = <0x48032000 0x80>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
};
timer3: timer@48034000 {
compatible = "ti,omap4430-timer";
reg = <0x48034000 0x80>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer3";
};
timer4: timer@48036000 {
compatible = "ti,omap4430-timer";
reg = <0x48036000 0x80>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer4";
};
timer5: timer@40138000 {
compatible = "ti,omap4430-timer";
reg = <0x40138000 0x80>,
<0x49038000 0x80>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer5";
ti,timer-dsp;
};
timer6: timer@4013a000 {
compatible = "ti,omap4430-timer";
reg = <0x4013a000 0x80>,
<0x4903a000 0x80>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer6";
ti,timer-dsp;
};
timer7: timer@4013c000 {
compatible = "ti,omap4430-timer";
reg = <0x4013c000 0x80>,
<0x4903c000 0x80>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer7";
ti,timer-dsp;
};
timer8: timer@4013e000 {
compatible = "ti,omap4430-timer";
reg = <0x4013e000 0x80>,
<0x4903e000 0x80>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer8";
ti,timer-pwm;
ti,timer-dsp;
};
timer9: timer@4803e000 {
compatible = "ti,omap4430-timer";
reg = <0x4803e000 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer9";
ti,timer-pwm;
};
timer10: timer@48086000 {
compatible = "ti,omap3430-timer";
reg = <0x48086000 0x80>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer10";
ti,timer-pwm;
};
timer11: timer@48088000 {
compatible = "ti,omap4430-timer";
reg = <0x48088000 0x80>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer11";
ti,timer-pwm;
};
usbhstll: usbhstll@4a062000 {
compatible = "ti,usbhs-tll";
reg = <0x4a062000 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "usb_tll_hs";
};
usbhshost: usbhshost@4a064000 {
compatible = "ti,usbhs-host";
reg = <0x4a064000 0x800>;
ti,hwmods = "usb_host_hs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbhsohci: ohci@4a064800 {
compatible = "ti,ohci-omap3", "usb-ohci";
reg = <0x4a064800 0x400>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
};
usbhsehci: ehci@4a064c00 {
compatible = "ti,ehci-omap", "usb-ehci";
reg = <0x4a064c00 0x400>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
};
omap_control_usb2phy: control-phy@4a002300 {
compatible = "ti,control-phy-usb2";
reg = <0x4a002300 0x4>;
reg-names = "power";
};
omap_control_usbotg: control-phy@4a00233c {
compatible = "ti,control-phy-otghs";
reg = <0x4a00233c 0x4>;
reg-names = "otghs_control";
};
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = "ti,omap4-musb";
reg = <0x4a0ab000 0x7ff>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc", "dma";
ti,hwmods = "usb_otg_hs";
usb-phy = <&usb2_phy>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
multipoint = <1>;
num-eps = <16>;
ram-bits = <12>;
ctrl-module = <&omap_control_usbotg>;
};
aes: aes@4b501000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes";
reg = <0x4b501000 0xa0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 111>, <&sdma 110>;
dma-names = "tx", "rx";
};
des: des@480a5000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x480a5000 0xa0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 117>, <&sdma 116>;
dma-names = "tx", "rx";
};
};
};
/include/ "omap44xx-clocks.dtsi"
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