307 lines
8.6 KiB
C
307 lines
8.6 KiB
C
#ifndef __PPC64_SYSTEM_H
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#define __PPC64_SYSTEM_H
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/compiler.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/hw_irq.h>
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#include <asm/memory.h>
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/*
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* Memory barrier.
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* The sync instruction guarantees that all memory accesses initiated
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* by this processor have been performed (with respect to all other
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* mechanisms that access memory). The eieio instruction is a barrier
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* providing an ordering (separately) for (a) cacheable stores and (b)
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* loads and stores to non-cacheable memory (e.g. I/O devices).
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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* read_barrier_depends() prevents data-dependent loads being reordered
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* across this point (nop on PPC).
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*
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* We have to use the sync instructions for mb(), since lwsync doesn't
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* order loads with respect to previous stores. Lwsync is fine for
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* rmb(), though.
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* For wmb(), we use sync since wmb is used in drivers to order
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* stores to system memory with respect to writes to the device.
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* However, smp_wmb() can be a lighter-weight eieio barrier on
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* SMP since it is only used to order updates to system memory.
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*/
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#define mb() __asm__ __volatile__ ("sync" : : : "memory")
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#define rmb() __asm__ __volatile__ ("lwsync" : : : "memory")
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#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
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#define set_wmb(var, value) do { var = value; smp_wmb(); } while (0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() __asm__ __volatile__("": : :"memory")
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#define smp_rmb() __asm__ __volatile__("": : :"memory")
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#define smp_wmb() __asm__ __volatile__("": : :"memory")
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#define smp_read_barrier_depends() do { } while(0)
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#endif /* CONFIG_SMP */
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#ifdef __KERNEL__
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struct task_struct;
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struct pt_regs;
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#ifdef CONFIG_DEBUGGER
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extern int (*__debugger)(struct pt_regs *regs);
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extern int (*__debugger_ipi)(struct pt_regs *regs);
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extern int (*__debugger_bpt)(struct pt_regs *regs);
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extern int (*__debugger_sstep)(struct pt_regs *regs);
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extern int (*__debugger_iabr_match)(struct pt_regs *regs);
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extern int (*__debugger_dabr_match)(struct pt_regs *regs);
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extern int (*__debugger_fault_handler)(struct pt_regs *regs);
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#define DEBUGGER_BOILERPLATE(__NAME) \
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static inline int __NAME(struct pt_regs *regs) \
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{ \
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if (unlikely(__ ## __NAME)) \
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return __ ## __NAME(regs); \
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return 0; \
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}
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DEBUGGER_BOILERPLATE(debugger)
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DEBUGGER_BOILERPLATE(debugger_ipi)
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DEBUGGER_BOILERPLATE(debugger_bpt)
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DEBUGGER_BOILERPLATE(debugger_sstep)
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DEBUGGER_BOILERPLATE(debugger_iabr_match)
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DEBUGGER_BOILERPLATE(debugger_dabr_match)
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DEBUGGER_BOILERPLATE(debugger_fault_handler)
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#ifdef CONFIG_XMON
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extern void xmon_init(void);
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#endif
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#else
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static inline int debugger(struct pt_regs *regs) { return 0; }
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static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
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static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
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static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
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static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
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static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
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static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
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#endif
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extern int fix_alignment(struct pt_regs *regs);
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extern void bad_page_fault(struct pt_regs *regs, unsigned long address,
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int sig);
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extern void show_regs(struct pt_regs * regs);
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extern void low_hash_fault(struct pt_regs *regs, unsigned long address);
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extern int die(const char *str, struct pt_regs *regs, long err);
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extern int _get_PVR(void);
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extern void giveup_fpu(struct task_struct *);
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extern void disable_kernel_fp(void);
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extern void flush_fp_to_thread(struct task_struct *);
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extern void enable_kernel_fp(void);
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extern void giveup_altivec(struct task_struct *);
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extern void disable_kernel_altivec(void);
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extern void enable_kernel_altivec(void);
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extern int emulate_altivec(struct pt_regs *);
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extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
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extern void cvt_df(double *from, float *to, unsigned long *fpscr);
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#ifdef CONFIG_ALTIVEC
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extern void flush_altivec_to_thread(struct task_struct *);
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#else
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static inline void flush_altivec_to_thread(struct task_struct *t)
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{
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}
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#endif
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extern int mem_init_done; /* set on boot once kmalloc can be called */
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/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
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extern unsigned char e2a(unsigned char);
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extern struct task_struct *__switch_to(struct task_struct *,
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struct task_struct *);
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#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
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struct thread_struct;
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extern struct task_struct * _switch(struct thread_struct *prev,
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struct thread_struct *next);
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static inline int __is_processor(unsigned long pv)
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{
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unsigned long pvr;
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asm("mfspr %0, 0x11F" : "=r" (pvr));
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return(PVR_VER(pvr) == pv);
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}
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/*
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* Atomic exchange
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*
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* Changes the memory location '*ptr' to be val and returns
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* the previous value stored there.
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*
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* Inline asm pulled from arch/ppc/kernel/misc.S so ppc64
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* is more like most of the other architectures.
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*/
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static __inline__ unsigned long
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__xchg_u32(volatile int *m, unsigned long val)
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{
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unsigned long dummy;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%3 # __xchg_u32\n\
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stwcx. %2,0,%3\n\
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2: bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (dummy), "=m" (*m)
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: "r" (val), "r" (m)
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: "cc", "memory");
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return (dummy);
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}
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static __inline__ unsigned long
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__xchg_u64(volatile long *m, unsigned long val)
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{
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unsigned long dummy;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: ldarx %0,0,%3 # __xchg_u64\n\
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stdcx. %2,0,%3\n\
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2: bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (dummy), "=m" (*m)
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: "r" (val), "r" (m)
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: "cc", "memory");
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return (dummy);
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}
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/*
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* This function doesn't exist, so you'll get a linker error
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* if something tries to do an invalid xchg().
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*/
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extern void __xchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__xchg(volatile void *ptr, unsigned long x, int size)
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{
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switch (size) {
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case 4:
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return __xchg_u32(ptr, x);
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case 8:
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return __xchg_u64(ptr, x);
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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#define xchg(ptr,x) \
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({ \
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__typeof__(*(ptr)) _x_ = (x); \
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(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
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})
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#define tas(ptr) (xchg((ptr),1))
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#define __HAVE_ARCH_CMPXCHG 1
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static __inline__ unsigned long
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__cmpxchg_u32(volatile int *p, int old, int new)
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{
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unsigned int prev;
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__asm__ __volatile__ (
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EIEIO_ON_SMP
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"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
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cmpw 0,%0,%3\n\
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bne- 2f\n\
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stwcx. %4,0,%2\n\
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bne- 1b"
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ISYNC_ON_SMP
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"\n\
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2:"
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: "=&r" (prev), "=m" (*p)
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: "r" (p), "r" (old), "r" (new), "m" (*p)
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: "cc", "memory");
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return prev;
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}
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static __inline__ unsigned long
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__cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new)
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{
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unsigned long prev;
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__asm__ __volatile__ (
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EIEIO_ON_SMP
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"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
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cmpd 0,%0,%3\n\
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bne- 2f\n\
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stdcx. %4,0,%2\n\
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bne- 1b"
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ISYNC_ON_SMP
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"\n\
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2:"
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: "=&r" (prev), "=m" (*p)
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: "r" (p), "r" (old), "r" (new), "m" (*p)
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: "cc", "memory");
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return prev;
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}
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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case 8:
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return __cmpxchg_u64(ptr, old, new);
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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/*
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* We handle most unaligned accesses in hardware. On the other hand
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* unaligned DMA can be very expensive on some ppc64 IO chips (it does
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* powers of 2 writes until it reaches sufficient alignment).
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*
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* Based on this we disable the IP header alignment in network drivers.
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*/
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#define NET_IP_ALIGN 0
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif
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