322 lines
8.1 KiB
C
322 lines
8.1 KiB
C
/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/nl80211.h>
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#include <linux/pci.h>
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#include "ath9k.h"
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static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
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{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
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{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
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{ 0 }
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};
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/* return bus cachesize in 4B word units */
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static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
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{
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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u8 u8tmp;
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pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
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*csz = (int)u8tmp;
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/*
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* This check was put in to avoid "unplesant" consequences if
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* the bootrom has not fully initialized all PCI devices.
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* Sometimes the cache line size register is not set
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*/
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if (*csz == 0)
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*csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
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}
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static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
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{
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struct ath_hw *ah = (struct ath_hw *) common->ah;
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common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
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if (!ath9k_hw_wait(ah,
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AR_EEPROM_STATUS_DATA,
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AR_EEPROM_STATUS_DATA_BUSY |
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AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
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AH_WAIT_TIMEOUT)) {
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return false;
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}
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*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
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AR_EEPROM_STATUS_DATA_VAL);
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return true;
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}
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/*
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* Bluetooth coexistance requires disabling ASPM.
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*/
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static void ath_pci_bt_coex_prep(struct ath_common *common)
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{
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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struct pci_dev *pdev = to_pci_dev(sc->dev);
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u8 aspm;
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if (!pdev->is_pcie)
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return;
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pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
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aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
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pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
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}
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static const struct ath_bus_ops ath_pci_bus_ops = {
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.ath_bus_type = ATH_PCI,
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.read_cachesize = ath_pci_read_cachesize,
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.eeprom_read = ath_pci_eeprom_read,
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.bt_coex_prep = ath_pci_bt_coex_prep,
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};
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static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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void __iomem *mem;
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struct ath_wiphy *aphy;
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struct ath_softc *sc;
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struct ieee80211_hw *hw;
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u8 csz;
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u16 subsysid;
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u32 val;
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int ret = 0;
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char hw_name[64];
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if (pci_enable_device(pdev))
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return -EIO;
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ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (ret) {
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printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
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goto err_dma;
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}
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ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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if (ret) {
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printk(KERN_ERR "ath9k: 32-bit DMA consistent "
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"DMA enable failed\n");
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goto err_dma;
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}
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/*
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* Cache line size is used to size and align various
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* structures used to communicate with the hardware.
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*/
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
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if (csz == 0) {
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/*
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* Linux 2.4.18 (at least) writes the cache line size
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* register as a 16-bit wide register which is wrong.
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* We must have this setup properly for rx buffer
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* DMA to work so force a reasonable value here if it
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* comes up zero.
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*/
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csz = L1_CACHE_BYTES / sizeof(u32);
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
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}
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/*
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* The default setting of latency timer yields poor results,
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* set it to the value used by other systems. It may be worth
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* tweaking this setting more.
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*/
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
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pci_set_master(pdev);
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/*
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* Disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state.
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*/
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pci_read_config_dword(pdev, 0x40, &val);
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if ((val & 0x0000ff00) != 0)
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pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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ret = pci_request_region(pdev, 0, "ath9k");
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if (ret) {
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dev_err(&pdev->dev, "PCI memory region reserve error\n");
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ret = -ENODEV;
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goto err_region;
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}
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mem = pci_iomap(pdev, 0, 0);
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if (!mem) {
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printk(KERN_ERR "PCI memory map error\n") ;
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ret = -EIO;
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goto err_iomap;
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}
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hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
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sizeof(struct ath_softc), &ath9k_ops);
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if (!hw) {
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dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
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ret = -ENOMEM;
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goto err_alloc_hw;
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}
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SET_IEEE80211_DEV(hw, &pdev->dev);
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pci_set_drvdata(pdev, hw);
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aphy = hw->priv;
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sc = (struct ath_softc *) (aphy + 1);
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aphy->sc = sc;
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aphy->hw = hw;
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sc->pri_wiphy = aphy;
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sc->hw = hw;
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sc->dev = &pdev->dev;
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sc->mem = mem;
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/* Will be cleared in ath9k_start() */
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sc->sc_flags |= SC_OP_INVALID;
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ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
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if (ret) {
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dev_err(&pdev->dev, "request_irq failed\n");
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goto err_irq;
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}
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sc->irq = pdev->irq;
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pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
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ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
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if (ret) {
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dev_err(&pdev->dev, "Failed to initialize device\n");
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goto err_init;
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}
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ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
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printk(KERN_INFO
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"%s: %s mem=0x%lx, irq=%d\n",
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wiphy_name(hw->wiphy),
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hw_name,
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(unsigned long)mem, pdev->irq);
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return 0;
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err_init:
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free_irq(sc->irq, sc);
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err_irq:
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ieee80211_free_hw(hw);
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err_alloc_hw:
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pci_iounmap(pdev, mem);
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err_iomap:
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pci_release_region(pdev, 0);
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err_region:
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/* Nothing */
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err_dma:
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pci_disable_device(pdev);
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return ret;
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}
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static void ath_pci_remove(struct pci_dev *pdev)
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{
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath_wiphy *aphy = hw->priv;
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struct ath_softc *sc = aphy->sc;
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void __iomem *mem = sc->mem;
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ath9k_deinit_device(sc);
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free_irq(sc->irq, sc);
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ieee80211_free_hw(sc->hw);
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pci_iounmap(pdev, mem);
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pci_disable_device(pdev);
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pci_release_region(pdev, 0);
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}
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#ifdef CONFIG_PM
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static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath_wiphy *aphy = hw->priv;
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struct ath_softc *sc = aphy->sc;
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ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
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pci_save_state(pdev);
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pci_disable_device(pdev);
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pci_set_power_state(pdev, PCI_D3hot);
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return 0;
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}
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static int ath_pci_resume(struct pci_dev *pdev)
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{
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath_wiphy *aphy = hw->priv;
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struct ath_softc *sc = aphy->sc;
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u32 val;
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int err;
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pci_restore_state(pdev);
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err = pci_enable_device(pdev);
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if (err)
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return err;
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/*
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* Suspend/Resume resets the PCI configuration space, so we have to
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* re-disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state
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*/
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pci_read_config_dword(pdev, 0x40, &val);
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if ((val & 0x0000ff00) != 0)
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pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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/* Enable LED */
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ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
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AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
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ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
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return 0;
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}
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#endif /* CONFIG_PM */
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MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
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static struct pci_driver ath_pci_driver = {
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.name = "ath9k",
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.id_table = ath_pci_id_table,
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.probe = ath_pci_probe,
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.remove = ath_pci_remove,
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#ifdef CONFIG_PM
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.suspend = ath_pci_suspend,
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.resume = ath_pci_resume,
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#endif /* CONFIG_PM */
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};
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int ath_pci_init(void)
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{
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return pci_register_driver(&ath_pci_driver);
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}
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void ath_pci_exit(void)
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{
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pci_unregister_driver(&ath_pci_driver);
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}
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