671 lines
16 KiB
C
671 lines
16 KiB
C
/*
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* Common code for SoCs starting with the S3C2443
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*
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* Copyright (c) 2007, 2010 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/regs-s3c2443-clock.h>
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#include <plat/clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq.h>
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static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
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{
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u32 ctrlbit = clk->ctrlbit;
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u32 con = __raw_readl(reg);
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if (enable)
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con |= ctrlbit;
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else
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con &= ~ctrlbit;
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__raw_writel(con, reg);
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return 0;
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}
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int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
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{
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return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
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}
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int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
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{
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return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
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}
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int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
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{
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return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
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}
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/* mpllref is a direct descendant of clk_xtal by default, but it is not
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* elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
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* such directly equating the two source clocks is impossible.
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*/
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static struct clk clk_mpllref = {
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.name = "mpllref",
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.parent = &clk_xtal,
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};
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static struct clk *clk_epllref_sources[] = {
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[0] = &clk_mpllref,
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[1] = &clk_mpllref,
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[2] = &clk_xtal,
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[3] = &clk_ext,
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};
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struct clksrc_clk clk_epllref = {
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.clk = {
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.name = "epllref",
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_epllref_sources,
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.nr_sources = ARRAY_SIZE(clk_epllref_sources),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
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};
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/* esysclk
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*
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* this is sourced from either the EPLL or the EPLLref clock
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*/
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static struct clk *clk_sysclk_sources[] = {
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[0] = &clk_epllref.clk,
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[1] = &clk_epll,
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};
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struct clksrc_clk clk_esysclk = {
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.clk = {
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.name = "esysclk",
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.parent = &clk_epll,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_sysclk_sources,
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.nr_sources = ARRAY_SIZE(clk_sysclk_sources),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
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};
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static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long div = __raw_readl(S3C2443_CLKDIV0);
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div &= S3C2443_CLKDIV0_EXTDIV_MASK;
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div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
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return parent_rate / (div + 1);
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}
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static struct clk clk_mdivclk = {
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.name = "mdivclk",
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.parent = &clk_mpllref,
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.ops = &(struct clk_ops) {
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.get_rate = s3c2443_getrate_mdivclk,
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},
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};
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static struct clk *clk_msysclk_sources[] = {
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[0] = &clk_mpllref,
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[1] = &clk_mpll,
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[2] = &clk_mdivclk,
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[3] = &clk_mpllref,
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};
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struct clksrc_clk clk_msysclk = {
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.clk = {
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.name = "msysclk",
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.parent = &clk_xtal,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_msysclk_sources,
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.nr_sources = ARRAY_SIZE(clk_msysclk_sources),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
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};
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/* prediv
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*
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* this divides the msysclk down to pass to h/p/etc.
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*/
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static unsigned long s3c2443_prediv_getrate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
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clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
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return rate / (clkdiv0 + 1);
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}
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static struct clk clk_prediv = {
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.name = "prediv",
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.parent = &clk_msysclk.clk,
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.ops = &(struct clk_ops) {
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.get_rate = s3c2443_prediv_getrate,
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},
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};
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/* hclk divider
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*
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* divides the prediv and provides the hclk.
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*/
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static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
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return rate / (clkdiv0 + 1);
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}
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static struct clk_ops clk_h_ops = {
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.get_rate = s3c2443_hclkdiv_getrate,
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};
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/* pclk divider
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*
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* divides the hclk and provides the pclk.
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*/
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static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
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clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0);
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return rate / (clkdiv0 + 1);
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}
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static struct clk_ops clk_p_ops = {
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.get_rate = s3c2443_pclkdiv_getrate,
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};
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/* armdiv
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*
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* this clock is sourced from msysclk and can have a number of
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* divider values applied to it to then be fed into armclk.
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*/
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static unsigned int *armdiv;
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static int nr_armdiv;
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static int armdivmask;
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static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent = clk_get_rate(clk->parent);
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unsigned long calc;
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unsigned best = 256; /* bigger than any value */
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unsigned div;
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int ptr;
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if (!nr_armdiv)
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return -EINVAL;
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for (ptr = 0; ptr < nr_armdiv; ptr++) {
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div = armdiv[ptr];
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if (div) {
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/* cpufreq provides 266mhz as 266666000 not 266666666 */
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calc = (parent / div / 1000) * 1000;
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if (calc <= rate && div < best)
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best = div;
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}
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}
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return parent / best;
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}
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static unsigned long s3c2443_armclk_getrate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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unsigned long clkcon0;
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int val;
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if (!nr_armdiv || !armdivmask)
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return -EINVAL;
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clkcon0 = __raw_readl(S3C2443_CLKDIV0);
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clkcon0 &= armdivmask;
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val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
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return rate / armdiv[val];
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}
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static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
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{
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unsigned long parent = clk_get_rate(clk->parent);
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unsigned long calc;
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unsigned div;
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unsigned best = 256; /* bigger than any value */
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int ptr;
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int val = -1;
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if (!nr_armdiv || !armdivmask)
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return -EINVAL;
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for (ptr = 0; ptr < nr_armdiv; ptr++) {
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div = armdiv[ptr];
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if (div) {
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/* cpufreq provides 266mhz as 266666000 not 266666666 */
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calc = (parent / div / 1000) * 1000;
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if (calc <= rate && div < best) {
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best = div;
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val = ptr;
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}
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}
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}
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if (val >= 0) {
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unsigned long clkcon0;
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clkcon0 = __raw_readl(S3C2443_CLKDIV0);
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clkcon0 &= ~armdivmask;
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clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
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__raw_writel(clkcon0, S3C2443_CLKDIV0);
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}
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return (val == -1) ? -EINVAL : 0;
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}
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static struct clk clk_armdiv = {
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.name = "armdiv",
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.parent = &clk_msysclk.clk,
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.ops = &(struct clk_ops) {
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.round_rate = s3c2443_armclk_roundrate,
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.get_rate = s3c2443_armclk_getrate,
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.set_rate = s3c2443_armclk_setrate,
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},
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};
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/* armclk
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*
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* this is the clock fed into the ARM core itself, from armdiv or from hclk.
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*/
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static struct clk *clk_arm_sources[] = {
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[0] = &clk_armdiv,
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[1] = &clk_h,
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};
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static struct clksrc_clk clk_arm = {
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.clk = {
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.name = "armclk",
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_arm_sources,
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.nr_sources = ARRAY_SIZE(clk_arm_sources),
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},
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.reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
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};
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/* usbhost
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*
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* usb host bus-clock, usually 48MHz to provide USB bus clock timing
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*/
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static struct clksrc_clk clk_usb_bus_host = {
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.clk = {
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.name = "usb-bus-host-parent",
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.parent = &clk_esysclk.clk,
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.ctrlbit = S3C2443_SCLKCON_USBHOST,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
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};
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/* common clksrc clocks */
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static struct clksrc_clk clksrc_clks[] = {
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{
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/* camera interface bus-clock, divided down from esysclk */
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.clk = {
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.name = "camif-upll", /* same as 2440 name */
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.parent = &clk_esysclk.clk,
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.ctrlbit = S3C2443_SCLKCON_CAMCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
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}, {
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.clk = {
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.name = "display-if",
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.parent = &clk_esysclk.clk,
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.ctrlbit = S3C2443_SCLKCON_DISPCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
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},
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};
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static struct clksrc_clk clk_esys_uart = {
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/* ART baud-rate clock sourced from esysclk via a divisor */
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.clk = {
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.name = "uartclk",
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.parent = &clk_esysclk.clk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
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};
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static struct clk clk_i2s_ext = {
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.name = "i2s-ext",
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};
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/* i2s_eplldiv
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*
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* This clock is the output from the I2S divisor of ESYSCLK, and is separate
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* from the mux that comes after it (cannot merge into one single clock)
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*/
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static struct clksrc_clk clk_i2s_eplldiv = {
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.clk = {
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.name = "i2s-eplldiv",
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.parent = &clk_esysclk.clk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
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};
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/* i2s-ref
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*
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* i2s bus reference clock, selectable from external, esysclk or epllref
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*
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* Note, this used to be two clocks, but was compressed into one.
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*/
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static struct clk *clk_i2s_srclist[] = {
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[0] = &clk_i2s_eplldiv.clk,
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[1] = &clk_i2s_ext,
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[2] = &clk_epllref.clk,
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[3] = &clk_epllref.clk,
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};
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static struct clksrc_clk clk_i2s = {
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.clk = {
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.name = "i2s-if",
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.ctrlbit = S3C2443_SCLKCON_I2SCLK,
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.enable = s3c2443_clkcon_enable_s,
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},
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.sources = &(struct clksrc_sources) {
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.sources = clk_i2s_srclist,
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.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
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};
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static struct clk init_clocks_off[] = {
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{
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.name = "iis",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_IIS,
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}, {
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.name = "hsspi",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_HSSPI,
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}, {
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.name = "adc",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_ADC,
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}, {
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.name = "i2c",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_IIC,
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}
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};
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static struct clk init_clocks[] = {
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{
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA0,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA1,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA2,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA3,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA4,
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}, {
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.name = "dma",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_DMA5,
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}, {
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.name = "gpio",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_GPIO,
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}, {
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.name = "usb-host",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_USBH,
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}, {
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.name = "usb-device",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_USBD,
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}, {
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.name = "lcd",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_LCDC,
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}, {
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.name = "timers",
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.parent = &clk_p,
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.enable = s3c2443_clkcon_enable_p,
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.ctrlbit = S3C2443_PCLKCON_PWMT,
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}, {
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.name = "cfc",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_CFC,
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}, {
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.name = "ssmc",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2443_HCLKCON_SSMC,
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}, {
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.name = "uart",
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.devname = "s3c2440-uart.0",
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_UART0,
|
|
}, {
|
|
.name = "uart",
|
|
.devname = "s3c2440-uart.1",
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_UART1,
|
|
}, {
|
|
.name = "uart",
|
|
.devname = "s3c2440-uart.2",
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_UART2,
|
|
}, {
|
|
.name = "uart",
|
|
.devname = "s3c2440-uart.3",
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_UART3,
|
|
}, {
|
|
.name = "rtc",
|
|
.parent = &clk_p,
|
|
.enable = s3c2443_clkcon_enable_p,
|
|
.ctrlbit = S3C2443_PCLKCON_RTC,
|
|
}, {
|
|
.name = "watchdog",
|
|
.parent = &clk_p,
|
|
.ctrlbit = S3C2443_PCLKCON_WDT,
|
|
}, {
|
|
.name = "ac97",
|
|
.parent = &clk_p,
|
|
.ctrlbit = S3C2443_PCLKCON_AC97,
|
|
}, {
|
|
.name = "nand",
|
|
.parent = &clk_h,
|
|
}, {
|
|
.name = "usb-bus-host",
|
|
.parent = &clk_usb_bus_host.clk,
|
|
}
|
|
};
|
|
|
|
static struct clk hsmmc1_clk = {
|
|
.name = "hsmmc",
|
|
.devname = "s3c-sdhci.1",
|
|
.parent = &clk_h,
|
|
.enable = s3c2443_clkcon_enable_h,
|
|
.ctrlbit = S3C2443_HCLKCON_HSMMC,
|
|
};
|
|
|
|
/* EPLLCON compatible enough to get on/off information */
|
|
|
|
void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
|
|
{
|
|
unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
|
|
unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
|
|
struct clk *xtal_clk;
|
|
unsigned long xtal;
|
|
unsigned long pll;
|
|
int ptr;
|
|
|
|
xtal_clk = clk_get(NULL, "xtal");
|
|
xtal = clk_get_rate(xtal_clk);
|
|
clk_put(xtal_clk);
|
|
|
|
pll = get_mpll(mpllcon, xtal);
|
|
clk_msysclk.clk.rate = pll;
|
|
clk_mpll.rate = pll;
|
|
|
|
printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
|
|
(mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
|
|
print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)),
|
|
print_mhz(clk_get_rate(&clk_h)),
|
|
print_mhz(clk_get_rate(&clk_p)));
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
|
|
s3c_set_clksrc(&clksrc_clks[ptr], true);
|
|
|
|
/* ensure usb bus clock is within correct rate of 48MHz */
|
|
|
|
if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
|
|
printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
|
|
clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
|
|
}
|
|
|
|
printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
|
|
(epllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
|
|
print_mhz(clk_get_rate(&clk_epll)),
|
|
print_mhz(clk_get_rate(&clk_usb_bus)));
|
|
}
|
|
|
|
static struct clk *clks[] __initdata = {
|
|
&clk_prediv,
|
|
&clk_mpllref,
|
|
&clk_mdivclk,
|
|
&clk_ext,
|
|
&clk_epll,
|
|
&clk_usb_bus,
|
|
&clk_armdiv,
|
|
&hsmmc1_clk,
|
|
};
|
|
|
|
static struct clksrc_clk *clksrcs[] __initdata = {
|
|
&clk_i2s_eplldiv,
|
|
&clk_i2s,
|
|
&clk_usb_bus_host,
|
|
&clk_epllref,
|
|
&clk_esysclk,
|
|
&clk_msysclk,
|
|
&clk_arm,
|
|
};
|
|
|
|
static struct clk_lookup s3c2443_clk_lookup[] = {
|
|
CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
|
|
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
|
|
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
|
|
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
|
|
};
|
|
|
|
void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
|
|
unsigned int *divs, int nr_divs,
|
|
int divmask)
|
|
{
|
|
int ptr;
|
|
|
|
armdiv = divs;
|
|
nr_armdiv = nr_divs;
|
|
armdivmask = divmask;
|
|
|
|
/* s3c2443 parents h clock from prediv */
|
|
clk_h.parent = &clk_prediv;
|
|
clk_h.ops = &clk_h_ops;
|
|
|
|
/* and p clock from h clock */
|
|
clk_p.parent = &clk_h;
|
|
clk_p.ops = &clk_p_ops;
|
|
|
|
clk_usb_bus.parent = &clk_usb_bus_host.clk;
|
|
clk_epll.parent = &clk_epllref.clk;
|
|
|
|
s3c24xx_register_baseclocks(xtal);
|
|
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
|
|
|
|
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
|
|
s3c_register_clksrc(clksrcs[ptr], 1);
|
|
|
|
s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
|
|
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
|
|
|
/* See s3c2443/etc notes on disabling clocks at init time */
|
|
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
|
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
|
clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
|
|
|
|
s3c2443_common_setup_clocks(get_mpll);
|
|
}
|