409 lines
8.1 KiB
C
409 lines
8.1 KiB
C
/*
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* Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
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*
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* Copyright (c) 2003 Intracom S.A.
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* by Pantelis Antoniou <panto@intracom.gr>
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*
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* 2005 (c) MontaVista Software, Inc.
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/bitops.h>
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#include <linux/platform_device.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include "fs_enet.h"
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static int bitbang_prep_bit(u8 **datp, u8 *mskp,
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struct fs_mii_bit *mii_bit)
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{
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void *dat;
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int adv;
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u8 msk;
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dat = (void*) mii_bit->offset;
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adv = mii_bit->bit >> 3;
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dat = (char *)dat + adv;
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msk = 1 << (7 - (mii_bit->bit & 7));
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*datp = dat;
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*mskp = msk;
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return 0;
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}
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static inline void bb_set(u8 *p, u8 m)
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{
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out_8(p, in_8(p) | m);
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}
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static inline void bb_clr(u8 *p, u8 m)
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{
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out_8(p, in_8(p) & ~m);
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}
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static inline int bb_read(u8 *p, u8 m)
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{
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return (in_8(p) & m) != 0;
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}
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static inline void mdio_active(struct bb_info *bitbang)
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{
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bb_set(bitbang->mdio_dir, bitbang->mdio_dir_msk);
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}
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static inline void mdio_tristate(struct bb_info *bitbang )
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{
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bb_clr(bitbang->mdio_dir, bitbang->mdio_dir_msk);
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}
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static inline int mdio_read(struct bb_info *bitbang )
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{
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return bb_read(bitbang->mdio_dat, bitbang->mdio_dat_msk);
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}
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static inline void mdio(struct bb_info *bitbang , int what)
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{
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if (what)
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bb_set(bitbang->mdio_dat, bitbang->mdio_dat_msk);
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else
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bb_clr(bitbang->mdio_dat, bitbang->mdio_dat_msk);
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}
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static inline void mdc(struct bb_info *bitbang , int what)
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{
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if (what)
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bb_set(bitbang->mdc_dat, bitbang->mdc_msk);
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else
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bb_clr(bitbang->mdc_dat, bitbang->mdc_msk);
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}
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static inline void mii_delay(struct bb_info *bitbang )
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{
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udelay(bitbang->delay);
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}
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/* Utility to send the preamble, address, and register (common to read and write). */
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static void bitbang_pre(struct bb_info *bitbang , int read, u8 addr, u8 reg)
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{
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int j;
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/*
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* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
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* The IEEE spec says this is a PHY optional requirement. The AMD
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* 79C874 requires one after power up and one after a MII communications
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* error. This means that we are doing more preambles than we need,
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* but it is safer and will be much more robust.
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*/
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mdio_active(bitbang);
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mdio(bitbang, 1);
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for (j = 0; j < 32; j++) {
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mdc(bitbang, 0);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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}
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/* send the start bit (01) and the read opcode (10) or write (10) */
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mdc(bitbang, 0);
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mdio(bitbang, 0);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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mdc(bitbang, 0);
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mdio(bitbang, 1);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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mdc(bitbang, 0);
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mdio(bitbang, read);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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mdc(bitbang, 0);
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mdio(bitbang, !read);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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/* send the PHY address */
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for (j = 0; j < 5; j++) {
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mdc(bitbang, 0);
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mdio(bitbang, (addr & 0x10) != 0);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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addr <<= 1;
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}
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/* send the register address */
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for (j = 0; j < 5; j++) {
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mdc(bitbang, 0);
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mdio(bitbang, (reg & 0x10) != 0);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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reg <<= 1;
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}
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}
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static int fs_enet_mii_bb_read(struct mii_bus *bus , int phy_id, int location)
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{
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u16 rdreg;
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int ret, j;
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u8 addr = phy_id & 0xff;
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u8 reg = location & 0xff;
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struct bb_info* bitbang = bus->priv;
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bitbang_pre(bitbang, 1, addr, reg);
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/* tri-state our MDIO I/O pin so we can read */
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mdc(bitbang, 0);
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mdio_tristate(bitbang);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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/* check the turnaround bit: the PHY should be driving it to zero */
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if (mdio_read(bitbang) != 0) {
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/* PHY didn't drive TA low */
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for (j = 0; j < 32; j++) {
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mdc(bitbang, 0);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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}
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ret = -1;
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goto out;
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}
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mdc(bitbang, 0);
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mii_delay(bitbang);
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/* read 16 bits of register data, MSB first */
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rdreg = 0;
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for (j = 0; j < 16; j++) {
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mdc(bitbang, 1);
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mii_delay(bitbang);
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rdreg <<= 1;
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rdreg |= mdio_read(bitbang);
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mdc(bitbang, 0);
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mii_delay(bitbang);
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}
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mdc(bitbang, 1);
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mii_delay(bitbang);
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mdc(bitbang, 0);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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ret = rdreg;
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out:
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return ret;
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}
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static int fs_enet_mii_bb_write(struct mii_bus *bus, int phy_id, int location, u16 val)
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{
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int j;
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struct bb_info* bitbang = bus->priv;
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u8 addr = phy_id & 0xff;
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u8 reg = location & 0xff;
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u16 value = val & 0xffff;
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bitbang_pre(bitbang, 0, addr, reg);
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/* send the turnaround (10) */
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mdc(bitbang, 0);
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mdio(bitbang, 1);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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mdc(bitbang, 0);
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mdio(bitbang, 0);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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/* write 16 bits of register data, MSB first */
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for (j = 0; j < 16; j++) {
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mdc(bitbang, 0);
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mdio(bitbang, (value & 0x8000) != 0);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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value <<= 1;
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}
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/*
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* Tri-state the MDIO line.
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*/
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mdio_tristate(bitbang);
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mdc(bitbang, 0);
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mii_delay(bitbang);
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mdc(bitbang, 1);
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mii_delay(bitbang);
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return 0;
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}
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static int fs_enet_mii_bb_reset(struct mii_bus *bus)
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{
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/*nothing here - dunno how to reset it*/
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return 0;
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}
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static int fs_mii_bitbang_init(struct bb_info *bitbang, struct fs_mii_bb_platform_info* fmpi)
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{
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int r;
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bitbang->delay = fmpi->delay;
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r = bitbang_prep_bit(&bitbang->mdio_dir,
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&bitbang->mdio_dir_msk,
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&fmpi->mdio_dir);
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if (r != 0)
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return r;
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r = bitbang_prep_bit(&bitbang->mdio_dat,
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&bitbang->mdio_dat_msk,
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&fmpi->mdio_dat);
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if (r != 0)
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return r;
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r = bitbang_prep_bit(&bitbang->mdc_dat,
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&bitbang->mdc_msk,
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&fmpi->mdc_dat);
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if (r != 0)
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return r;
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return 0;
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}
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static int __devinit fs_enet_mdio_probe(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct fs_mii_bb_platform_info *pdata;
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struct mii_bus *new_bus;
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struct bb_info *bitbang;
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int err = 0;
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if (NULL == dev)
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return -EINVAL;
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new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
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if (NULL == new_bus)
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return -ENOMEM;
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bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
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if (NULL == bitbang)
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return -ENOMEM;
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new_bus->name = "BB MII Bus",
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new_bus->read = &fs_enet_mii_bb_read,
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new_bus->write = &fs_enet_mii_bb_write,
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new_bus->reset = &fs_enet_mii_bb_reset,
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new_bus->id = pdev->id;
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new_bus->phy_mask = ~0x9;
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pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
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if (NULL == pdata) {
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printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
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return -ENODEV;
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}
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/*set up workspace*/
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fs_mii_bitbang_init(bitbang, pdata);
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new_bus->priv = bitbang;
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new_bus->irq = pdata->irq;
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new_bus->dev = dev;
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dev_set_drvdata(dev, new_bus);
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err = mdiobus_register(new_bus);
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if (0 != err) {
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printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
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new_bus->name);
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goto bus_register_fail;
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}
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return 0;
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bus_register_fail:
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kfree(bitbang);
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kfree(new_bus);
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return err;
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}
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static int fs_enet_mdio_remove(struct device *dev)
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{
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struct mii_bus *bus = dev_get_drvdata(dev);
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mdiobus_unregister(bus);
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dev_set_drvdata(dev, NULL);
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iounmap((void *) (&bus->priv));
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bus->priv = NULL;
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kfree(bus);
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return 0;
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}
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static struct device_driver fs_enet_bb_mdio_driver = {
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.name = "fsl-bb-mdio",
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.bus = &platform_bus_type,
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.probe = fs_enet_mdio_probe,
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.remove = fs_enet_mdio_remove,
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};
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int fs_enet_mdio_bb_init(void)
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{
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return driver_register(&fs_enet_bb_mdio_driver);
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}
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void fs_enet_mdio_bb_exit(void)
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{
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driver_unregister(&fs_enet_bb_mdio_driver);
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}
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