703 lines
16 KiB
C
703 lines
16 KiB
C
#ifndef _ASM_M32R_BITOPS_H
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#define _ASM_M32R_BITOPS_H
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/*
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* linux/include/asm-m32r/bitops.h
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*
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* Copyright 1992, Linus Torvalds.
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*
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* M32R version:
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* Copyright (C) 2001, 2002 Hitoshi Yamamoto
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* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
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*/
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#include <linux/config.h>
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#include <linux/compiler.h>
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#include <asm/assembler.h>
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#include <asm/system.h>
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#include <asm/byteorder.h>
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#include <asm/types.h>
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/*
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* These have to be done with inline assembly: that way the bit-setting
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* is guaranteed to be atomic. All bit operations return 0 if the bit
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* was cleared before the operation and != 0 if it was not.
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*
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void set_bit(int nr, volatile void * addr)
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{
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__u32 mask;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r6", "%1")
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M32R_LOCK" %0, @%1; \n\t"
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"or %0, %2; \n\t"
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M32R_UNLOCK" %0, @%1; \n\t"
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: "=&r" (tmp)
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: "r" (a), "r" (mask)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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local_irq_restore(flags);
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}
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/**
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* __set_bit - Set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike set_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __inline__ void __set_bit(int nr, volatile void * addr)
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{
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__u32 mask;
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volatile __u32 *a = addr;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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*a |= mask;
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static __inline__ void clear_bit(int nr, volatile void * addr)
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{
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__u32 mask;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r6", "%1")
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M32R_LOCK" %0, @%1; \n\t"
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"and %0, %2; \n\t"
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M32R_UNLOCK" %0, @%1; \n\t"
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: "=&r" (tmp)
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: "r" (a), "r" (~mask)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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local_irq_restore(flags);
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}
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static __inline__ void __clear_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask;
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volatile unsigned long *a = addr;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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*a &= ~mask;
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}
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#define smp_mb__before_clear_bit() barrier()
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#define smp_mb__after_clear_bit() barrier()
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/**
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __inline__ void __change_bit(int nr, volatile void * addr)
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{
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__u32 mask;
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volatile __u32 *a = addr;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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*a ^= mask;
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static __inline__ void change_bit(int nr, volatile void * addr)
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{
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__u32 mask;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r6", "%1")
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M32R_LOCK" %0, @%1; \n\t"
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"xor %0, %2; \n\t"
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M32R_UNLOCK" %0, @%1; \n\t"
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: "=&r" (tmp)
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: "r" (a), "r" (mask)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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local_irq_restore(flags);
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_set_bit(int nr, volatile void * addr)
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{
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__u32 mask, oldbit;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "%1", "%2")
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M32R_LOCK" %0, @%2; \n\t"
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"mv %1, %0; \n\t"
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"and %0, %3; \n\t"
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"or %1, %3; \n\t"
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M32R_UNLOCK" %1, @%2; \n\t"
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: "=&r" (oldbit), "=&r" (tmp)
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: "r" (a), "r" (mask)
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: "memory"
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);
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local_irq_restore(flags);
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return (oldbit != 0);
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}
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/**
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* __test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
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{
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__u32 mask, oldbit;
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volatile __u32 *a = addr;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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oldbit = (*a & mask);
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*a |= mask;
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return (oldbit != 0);
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
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{
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__u32 mask, oldbit;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "%1", "%3")
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M32R_LOCK" %0, @%3; \n\t"
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"mv %1, %0; \n\t"
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"and %0, %2; \n\t"
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"not %2, %2; \n\t"
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"and %1, %2; \n\t"
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M32R_UNLOCK" %1, @%3; \n\t"
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: "=&r" (oldbit), "=&r" (tmp), "+r" (mask)
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: "r" (a)
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: "memory"
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);
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local_irq_restore(flags);
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return (oldbit != 0);
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}
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/**
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* __test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
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{
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__u32 mask, oldbit;
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volatile __u32 *a = addr;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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oldbit = (*a & mask);
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*a &= ~mask;
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return (oldbit != 0);
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}
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/* WARNING: non atomic and it can be reordered! */
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static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
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{
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__u32 mask, oldbit;
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volatile __u32 *a = addr;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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oldbit = (*a & mask);
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*a ^= mask;
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return (oldbit != 0);
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static __inline__ int test_and_change_bit(int nr, volatile void * addr)
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{
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__u32 mask, oldbit;
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volatile __u32 *a = addr;
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unsigned long flags;
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unsigned long tmp;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "%1", "%2")
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M32R_LOCK" %0, @%2; \n\t"
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"mv %1, %0; \n\t"
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"and %0, %3; \n\t"
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"xor %1, %3; \n\t"
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M32R_UNLOCK" %1, @%2; \n\t"
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: "=&r" (oldbit), "=&r" (tmp)
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: "r" (a), "r" (mask)
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: "memory"
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);
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local_irq_restore(flags);
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return (oldbit != 0);
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}
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/**
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* test_bit - Determine whether a bit is set
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* @nr: bit number to test
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* @addr: Address to start counting from
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*/
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static __inline__ int test_bit(int nr, const volatile void * addr)
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{
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__u32 mask;
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const volatile __u32 *a = addr;
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a += (nr >> 5);
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mask = (1 << (nr & 0x1F));
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return ((*a & mask) != 0);
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}
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/**
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* ffz - find first zero in word.
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* @word: The word to search
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*
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* Undefined if no zero exists, so code should check against ~0UL first.
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*/
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static __inline__ unsigned long ffz(unsigned long word)
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{
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int k;
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word = ~word;
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k = 0;
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if (!(word & 0x0000ffff)) { k += 16; word >>= 16; }
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if (!(word & 0x000000ff)) { k += 8; word >>= 8; }
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if (!(word & 0x0000000f)) { k += 4; word >>= 4; }
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if (!(word & 0x00000003)) { k += 2; word >>= 2; }
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if (!(word & 0x00000001)) { k += 1; }
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return k;
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}
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/**
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* find_first_zero_bit - find the first zero bit in a memory region
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* @addr: The address to start the search at
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* @size: The maximum size to search
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*
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* Returns the bit-number of the first zero bit, not the number of the byte
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* containing a bit.
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*/
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#define find_first_zero_bit(addr, size) \
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find_next_zero_bit((addr), (size), 0)
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/**
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* find_next_zero_bit - find the first zero bit in a memory region
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* @addr: The address to base the search on
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* @offset: The bitnumber to start searching at
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* @size: The maximum size to search
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*/
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static __inline__ int find_next_zero_bit(const unsigned long *addr,
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int size, int offset)
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{
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const unsigned long *p = addr + (offset >> 5);
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unsigned long result = offset & ~31UL;
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unsigned long tmp;
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if (offset >= size)
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return size;
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size -= result;
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offset &= 31UL;
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if (offset) {
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tmp = *(p++);
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tmp |= ~0UL >> (32-offset);
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if (size < 32)
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goto found_first;
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if (~tmp)
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goto found_middle;
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size -= 32;
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result += 32;
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}
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while (size & ~31UL) {
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if (~(tmp = *(p++)))
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goto found_middle;
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result += 32;
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size -= 32;
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}
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if (!size)
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return result;
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tmp = *p;
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found_first:
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tmp |= ~0UL << size;
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found_middle:
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return result + ffz(tmp);
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}
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/**
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* __ffs - find first bit in word.
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* @word: The word to search
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*
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* Undefined if no bit exists, so code should check against 0 first.
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*/
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static __inline__ unsigned long __ffs(unsigned long word)
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{
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int k = 0;
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if (!(word & 0x0000ffff)) { k += 16; word >>= 16; }
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if (!(word & 0x000000ff)) { k += 8; word >>= 8; }
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if (!(word & 0x0000000f)) { k += 4; word >>= 4; }
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if (!(word & 0x00000003)) { k += 2; word >>= 2; }
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if (!(word & 0x00000001)) { k += 1;}
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return k;
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}
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/*
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* fls: find last bit set.
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*/
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#define fls(x) generic_fls(x)
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#ifdef __KERNEL__
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/*
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* Every architecture must define this function. It's the fastest
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* way of searching a 140-bit bitmap where the first 100 bits are
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* unlikely to be set. It's guaranteed that at least one of the 140
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* bits is cleared.
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*/
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static inline int sched_find_first_bit(unsigned long *b)
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{
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if (unlikely(b[0]))
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return __ffs(b[0]);
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if (unlikely(b[1]))
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return __ffs(b[1]) + 32;
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if (unlikely(b[2]))
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return __ffs(b[2]) + 64;
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if (b[3])
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return __ffs(b[3]) + 96;
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return __ffs(b[4]) + 128;
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}
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/**
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* find_next_bit - find the first set bit in a memory region
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* @addr: The address to base the search on
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* @offset: The bitnumber to start searching at
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* @size: The maximum size to search
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*/
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static inline unsigned long find_next_bit(const unsigned long *addr,
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unsigned long size, unsigned long offset)
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{
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unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
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unsigned int result = offset & ~31UL;
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unsigned int tmp;
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if (offset >= size)
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return size;
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size -= result;
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offset &= 31UL;
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if (offset) {
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tmp = *p++;
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tmp &= ~0UL << offset;
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if (size < 32)
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goto found_first;
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if (tmp)
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goto found_middle;
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size -= 32;
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result += 32;
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}
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while (size >= 32) {
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if ((tmp = *p++) != 0)
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goto found_middle;
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result += 32;
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size -= 32;
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}
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if (!size)
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return result;
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tmp = *p;
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found_first:
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tmp &= ~0UL >> (32 - size);
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if (tmp == 0UL) /* Are any bits set? */
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return result + size; /* Nope. */
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found_middle:
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return result + __ffs(tmp);
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}
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/**
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* find_first_bit - find the first set bit in a memory region
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* @addr: The address to start the search at
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* @size: The maximum size to search
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*
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* Returns the bit-number of the first set bit, not the number of the byte
|
|
* containing a bit.
|
|
*/
|
|
#define find_first_bit(addr, size) \
|
|
find_next_bit((addr), (size), 0)
|
|
|
|
/**
|
|
* ffs - find first bit set
|
|
* @x: the word to search
|
|
*
|
|
* This is defined the same way as
|
|
* the libc and compiler builtin ffs routines, therefore
|
|
* differs in spirit from the above ffz (man ffs).
|
|
*/
|
|
#define ffs(x) generic_ffs(x)
|
|
|
|
/**
|
|
* hweightN - returns the hamming weight of a N-bit word
|
|
* @x: the word to weigh
|
|
*
|
|
* The Hamming Weight of a number is the total number of bits set in it.
|
|
*/
|
|
|
|
#define hweight32(x) generic_hweight32(x)
|
|
#define hweight16(x) generic_hweight16(x)
|
|
#define hweight8(x) generic_hweight8(x)
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#ifdef __KERNEL__
|
|
|
|
/*
|
|
* ext2_XXXX function
|
|
* orig: include/asm-sh/bitops.h
|
|
*/
|
|
|
|
#ifdef __LITTLE_ENDIAN__
|
|
#define ext2_set_bit test_and_set_bit
|
|
#define ext2_clear_bit __test_and_clear_bit
|
|
#define ext2_test_bit test_bit
|
|
#define ext2_find_first_zero_bit find_first_zero_bit
|
|
#define ext2_find_next_zero_bit find_next_zero_bit
|
|
#else
|
|
static inline int ext2_set_bit(int nr, volatile void * addr)
|
|
{
|
|
__u8 mask, oldbit;
|
|
volatile __u8 *a = addr;
|
|
|
|
a += (nr >> 3);
|
|
mask = (1 << (nr & 0x07));
|
|
oldbit = (*a & mask);
|
|
*a |= mask;
|
|
|
|
return (oldbit != 0);
|
|
}
|
|
|
|
static inline int ext2_clear_bit(int nr, volatile void * addr)
|
|
{
|
|
__u8 mask, oldbit;
|
|
volatile __u8 *a = addr;
|
|
|
|
a += (nr >> 3);
|
|
mask = (1 << (nr & 0x07));
|
|
oldbit = (*a & mask);
|
|
*a &= ~mask;
|
|
|
|
return (oldbit != 0);
|
|
}
|
|
|
|
static inline int ext2_test_bit(int nr, const volatile void * addr)
|
|
{
|
|
__u32 mask;
|
|
const volatile __u8 *a = addr;
|
|
|
|
a += (nr >> 3);
|
|
mask = (1 << (nr & 0x07));
|
|
|
|
return ((mask & *a) != 0);
|
|
}
|
|
|
|
#define ext2_find_first_zero_bit(addr, size) \
|
|
ext2_find_next_zero_bit((addr), (size), 0)
|
|
|
|
static inline unsigned long ext2_find_next_zero_bit(void *addr,
|
|
unsigned long size, unsigned long offset)
|
|
{
|
|
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
|
|
unsigned long result = offset & ~31UL;
|
|
unsigned long tmp;
|
|
|
|
if (offset >= size)
|
|
return size;
|
|
size -= result;
|
|
offset &= 31UL;
|
|
if(offset) {
|
|
/* We hold the little endian value in tmp, but then the
|
|
* shift is illegal. So we could keep a big endian value
|
|
* in tmp, like this:
|
|
*
|
|
* tmp = __swab32(*(p++));
|
|
* tmp |= ~0UL >> (32-offset);
|
|
*
|
|
* but this would decrease preformance, so we change the
|
|
* shift:
|
|
*/
|
|
tmp = *(p++);
|
|
tmp |= __swab32(~0UL >> (32-offset));
|
|
if(size < 32)
|
|
goto found_first;
|
|
if(~tmp)
|
|
goto found_middle;
|
|
size -= 32;
|
|
result += 32;
|
|
}
|
|
while(size & ~31UL) {
|
|
if(~(tmp = *(p++)))
|
|
goto found_middle;
|
|
result += 32;
|
|
size -= 32;
|
|
}
|
|
if(!size)
|
|
return result;
|
|
tmp = *p;
|
|
|
|
found_first:
|
|
/* tmp is little endian, so we would have to swab the shift,
|
|
* see above. But then we have to swab tmp below for ffz, so
|
|
* we might as well do this here.
|
|
*/
|
|
return result + ffz(__swab32(tmp) | (~0UL << size));
|
|
found_middle:
|
|
return result + ffz(__swab32(tmp));
|
|
}
|
|
#endif
|
|
|
|
#define ext2_set_bit_atomic(lock, nr, addr) \
|
|
({ \
|
|
int ret; \
|
|
spin_lock(lock); \
|
|
ret = ext2_set_bit((nr), (addr)); \
|
|
spin_unlock(lock); \
|
|
ret; \
|
|
})
|
|
|
|
#define ext2_clear_bit_atomic(lock, nr, addr) \
|
|
({ \
|
|
int ret; \
|
|
spin_lock(lock); \
|
|
ret = ext2_clear_bit((nr), (addr)); \
|
|
spin_unlock(lock); \
|
|
ret; \
|
|
})
|
|
|
|
/* Bitmap functions for the minix filesystem. */
|
|
#define minix_test_and_set_bit(nr,addr) __test_and_set_bit(nr,addr)
|
|
#define minix_set_bit(nr,addr) __set_bit(nr,addr)
|
|
#define minix_test_and_clear_bit(nr,addr) __test_and_clear_bit(nr,addr)
|
|
#define minix_test_bit(nr,addr) test_bit(nr,addr)
|
|
#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* _ASM_M32R_BITOPS_H */
|