255 lines
6.2 KiB
C
255 lines
6.2 KiB
C
/* MN10300 Arch-specific interrupt handling
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/seq_file.h>
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#include <asm/setup.h>
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unsigned long __mn10300_irq_enabled_epsw = EPSW_IE | EPSW_IM_7;
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EXPORT_SYMBOL(__mn10300_irq_enabled_epsw);
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atomic_t irq_err_count;
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/*
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* MN10300 interrupt controller operations
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*/
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static void mn10300_cpupic_ack(unsigned int irq)
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{
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u16 tmp;
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*(volatile u8 *) &GxICR(irq) = GxICR_DETECT;
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tmp = GxICR(irq);
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}
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static void mn10300_cpupic_mask(unsigned int irq)
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{
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u16 tmp = GxICR(irq);
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GxICR(irq) = (tmp & GxICR_LEVEL);
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tmp = GxICR(irq);
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}
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static void mn10300_cpupic_mask_ack(unsigned int irq)
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{
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u16 tmp = GxICR(irq);
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GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
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tmp = GxICR(irq);
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}
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static void mn10300_cpupic_unmask(unsigned int irq)
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{
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u16 tmp = GxICR(irq);
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GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE;
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tmp = GxICR(irq);
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}
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static void mn10300_cpupic_unmask_clear(unsigned int irq)
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{
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/* the MN10300 PIC latches its interrupt request bit, even after the
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* device has ceased to assert its interrupt line and the interrupt
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* channel has been disabled in the PIC, so for level-triggered
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* interrupts we need to clear the request bit when we re-enable */
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u16 tmp = GxICR(irq);
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GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
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tmp = GxICR(irq);
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}
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/*
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* MN10300 PIC level-triggered IRQ handling.
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*
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* The PIC has no 'ACK' function per se. It is possible to clear individual
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* channel latches, but each latch relatches whether or not the channel is
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* masked, so we need to clear the latch when we unmask the channel.
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*
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* Also for this reason, we don't supply an ack() op (it's unused anyway if
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* mask_ack() is provided), and mask_ack() just masks.
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*/
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static struct irq_chip mn10300_cpu_pic_level = {
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.name = "cpu_l",
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.disable = mn10300_cpupic_mask,
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.enable = mn10300_cpupic_unmask_clear,
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.ack = NULL,
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.mask = mn10300_cpupic_mask,
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.mask_ack = mn10300_cpupic_mask,
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.unmask = mn10300_cpupic_unmask_clear,
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};
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/*
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* MN10300 PIC edge-triggered IRQ handling.
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*
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* We use the latch clearing function of the PIC as the 'ACK' function.
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*/
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static struct irq_chip mn10300_cpu_pic_edge = {
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.name = "cpu_e",
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.disable = mn10300_cpupic_mask,
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.enable = mn10300_cpupic_unmask,
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.ack = mn10300_cpupic_ack,
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.mask = mn10300_cpupic_mask,
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.mask_ack = mn10300_cpupic_mask_ack,
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.unmask = mn10300_cpupic_unmask,
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};
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(int irq)
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{
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printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
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}
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/*
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* change the level at which an IRQ executes
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* - must not be called whilst interrupts are being processed!
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*/
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void set_intr_level(int irq, u16 level)
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{
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u16 tmp;
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if (in_interrupt())
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BUG();
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tmp = GxICR(irq);
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GxICR(irq) = (tmp & GxICR_ENABLE) | level;
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tmp = GxICR(irq);
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}
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/*
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* mark an interrupt to be ACK'd after interrupt handlers have been run rather
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* than before
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* - see Documentation/mn10300/features.txt
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*/
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void set_intr_postackable(int irq)
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{
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set_irq_chip_and_handler(irq, &mn10300_cpu_pic_level,
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handle_level_irq);
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}
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/*
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* initialise the interrupt system
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*/
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void __init init_IRQ(void)
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{
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int irq;
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for (irq = 0; irq < NR_IRQS; irq++)
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if (irq_desc[irq].chip == &no_irq_chip)
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/* due to the PIC latching interrupt requests, even
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* when the IRQ is disabled, IRQ_PENDING is superfluous
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* and we can use handle_level_irq() for edge-triggered
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* interrupts */
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set_irq_chip_and_handler(irq, &mn10300_cpu_pic_edge,
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handle_level_irq);
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unit_init_IRQ();
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}
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/*
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* handle normal device IRQs
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*/
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asmlinkage void do_IRQ(void)
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{
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unsigned long sp, epsw, irq_disabled_epsw, old_irq_enabled_epsw;
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int irq;
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sp = current_stack_pointer();
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if (sp - (sp & ~(THREAD_SIZE - 1)) < STACK_WARN)
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BUG();
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/* make sure local_irq_enable() doesn't muck up the interrupt priority
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* setting in EPSW */
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old_irq_enabled_epsw = __mn10300_irq_enabled_epsw;
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local_save_flags(epsw);
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__mn10300_irq_enabled_epsw = EPSW_IE | (EPSW_IM & epsw);
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irq_disabled_epsw = EPSW_IE | MN10300_CLI_LEVEL;
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__IRQ_STAT(smp_processor_id(), __irq_count)++;
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irq_enter();
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for (;;) {
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/* ask the interrupt controller for the next IRQ to process
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* - the result we get depends on EPSW.IM
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*/
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irq = IAGR & IAGR_GN;
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if (!irq)
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break;
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local_irq_restore(irq_disabled_epsw);
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generic_handle_irq(irq >> 2);
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/* restore IRQ controls for IAGR access */
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local_irq_restore(epsw);
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}
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__mn10300_irq_enabled_epsw = old_irq_enabled_epsw;
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irq_exit();
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}
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/*
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* Display interrupt management information through /proc/interrupts
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*/
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int show_interrupts(struct seq_file *p, void *v)
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{
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int i = *(loff_t *) v, j, cpu;
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struct irqaction *action;
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unsigned long flags;
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switch (i) {
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/* display column title bar naming CPUs */
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case 0:
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seq_printf(p, " ");
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for (j = 0; j < NR_CPUS; j++)
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if (cpu_online(j))
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seq_printf(p, "CPU%d ", j);
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seq_putc(p, '\n');
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break;
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/* display information rows, one per active CPU */
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case 1 ... NR_IRQS - 1:
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raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (action) {
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seq_printf(p, "%3d: ", i);
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for_each_present_cpu(cpu)
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seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
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seq_printf(p, " %14s.%u", irq_desc[i].chip->name,
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(GxICR(i) & GxICR_LEVEL) >>
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GxICR_LEVEL_SHIFT);
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seq_printf(p, " %s", action->name);
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for (action = action->next;
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action;
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action = action->next)
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seq_printf(p, ", %s", action->name);
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seq_putc(p, '\n');
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}
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raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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break;
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/* polish off with NMI and error counters */
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case NR_IRQS:
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seq_printf(p, "NMI: ");
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for (j = 0; j < NR_CPUS; j++)
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if (cpu_online(j))
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seq_printf(p, "%10u ", nmi_count(j));
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seq_putc(p, '\n');
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seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
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break;
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}
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return 0;
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}
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