30 lines
813 B
C
30 lines
813 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/arm/include/asm/cache.h
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*/
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#ifndef __ASMARM_CACHE_H
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#define __ASMARM_CACHE_H
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#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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/*
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* Memory returned by kmalloc() may be used for DMA, so we must make
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* sure that all such allocations are cache aligned. Otherwise,
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* unrelated code may cause parts of the buffer to be read into the
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* cache before the transfer is done, causing old data to be seen by
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* the CPU.
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*/
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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/*
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* With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
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*/
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#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
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#define ARCH_SLAB_MINALIGN 8
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#endif
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#define __read_mostly __attribute__((__section__(".data..read_mostly")))
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#endif
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