497 lines
13 KiB
C
497 lines
13 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2007-2009 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include <linux/delay.h>
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#include <linux/rtnetlink.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include "efx.h"
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#include "mdio_10g.h"
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#include "nic.h"
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#include "phy.h"
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#include "regs.h"
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#include "workarounds.h"
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#include "selftest.h"
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/* We expect these MMDs to be in the package. */
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#define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
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MDIO_DEVS_PCS | \
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MDIO_DEVS_PHYXS | \
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MDIO_DEVS_AN)
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#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
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(1 << LOOPBACK_PCS) | \
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(1 << LOOPBACK_PMAPMD) | \
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(1 << LOOPBACK_PHYXS_WS))
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/* We complain if we fail to see the link partner as 10G capable this many
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* times in a row (must be > 1 as sampling the autoneg. registers is racy)
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*/
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#define MAX_BAD_LP_TRIES (5)
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/* Extended control register */
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#define PMA_PMD_XCONTROL_REG 49152
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#define PMA_PMD_EXT_GMII_EN_LBN 1
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#define PMA_PMD_EXT_GMII_EN_WIDTH 1
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#define PMA_PMD_EXT_CLK_OUT_LBN 2
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#define PMA_PMD_EXT_CLK_OUT_WIDTH 1
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#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
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#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
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#define PMA_PMD_EXT_CLK312_WIDTH 1
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#define PMA_PMD_EXT_LPOWER_LBN 12
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#define PMA_PMD_EXT_LPOWER_WIDTH 1
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#define PMA_PMD_EXT_ROBUST_LBN 14
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#define PMA_PMD_EXT_ROBUST_WIDTH 1
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#define PMA_PMD_EXT_SSR_LBN 15
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#define PMA_PMD_EXT_SSR_WIDTH 1
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/* extended status register */
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#define PMA_PMD_XSTATUS_REG 49153
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#define PMA_PMD_XSTAT_MDIX_LBN 14
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#define PMA_PMD_XSTAT_FLP_LBN (12)
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/* LED control register */
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#define PMA_PMD_LED_CTRL_REG 49159
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#define PMA_PMA_LED_ACTIVITY_LBN (3)
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/* LED function override register */
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#define PMA_PMD_LED_OVERR_REG 49161
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/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
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#define PMA_PMD_LED_LINK_LBN (0)
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#define PMA_PMD_LED_SPEED_LBN (2)
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#define PMA_PMD_LED_TX_LBN (4)
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#define PMA_PMD_LED_RX_LBN (6)
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/* Override settings */
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#define PMA_PMD_LED_AUTO (0) /* H/W control */
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#define PMA_PMD_LED_ON (1)
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#define PMA_PMD_LED_OFF (2)
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#define PMA_PMD_LED_FLASH (3)
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#define PMA_PMD_LED_MASK 3
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/* All LEDs under hardware control */
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/* Green and Amber under hardware control, Red off */
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#define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
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#define PMA_PMD_SPEED_ENABLE_REG 49192
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#define PMA_PMD_100TX_ADV_LBN 1
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#define PMA_PMD_100TX_ADV_WIDTH 1
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#define PMA_PMD_1000T_ADV_LBN 2
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#define PMA_PMD_1000T_ADV_WIDTH 1
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#define PMA_PMD_10000T_ADV_LBN 3
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#define PMA_PMD_10000T_ADV_WIDTH 1
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#define PMA_PMD_SPEED_LBN 4
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#define PMA_PMD_SPEED_WIDTH 4
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/* Misc register defines */
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#define PCS_CLOCK_CTRL_REG 55297
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#define PLL312_RST_N_LBN 2
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#define PCS_SOFT_RST2_REG 55302
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#define SERDES_RST_N_LBN 13
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#define XGXS_RST_N_LBN 12
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#define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
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#define CLK312_EN_LBN 3
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/* PHYXS registers */
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#define PHYXS_XCONTROL_REG 49152
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#define PHYXS_RESET_LBN 15
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#define PHYXS_RESET_WIDTH 1
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#define PHYXS_TEST1 (49162)
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#define LOOPBACK_NEAR_LBN (8)
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#define LOOPBACK_NEAR_WIDTH (1)
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/* Boot status register */
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#define PCS_BOOT_STATUS_REG 53248
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#define PCS_BOOT_FATAL_ERROR_LBN 0
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#define PCS_BOOT_PROGRESS_LBN 1
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#define PCS_BOOT_PROGRESS_WIDTH 2
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#define PCS_BOOT_PROGRESS_INIT 0
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#define PCS_BOOT_PROGRESS_WAIT_MDIO 1
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#define PCS_BOOT_PROGRESS_CHECKSUM 2
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#define PCS_BOOT_PROGRESS_JUMP 3
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#define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
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#define PCS_BOOT_CODE_STARTED_LBN 4
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/* 100M/1G PHY registers */
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#define GPHY_XCONTROL_REG 49152
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#define GPHY_ISOLATE_LBN 10
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#define GPHY_ISOLATE_WIDTH 1
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#define GPHY_DUPLEX_LBN 8
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#define GPHY_DUPLEX_WIDTH 1
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#define GPHY_LOOPBACK_NEAR_LBN 14
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#define GPHY_LOOPBACK_NEAR_WIDTH 1
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#define C22EXT_STATUS_REG 49153
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#define C22EXT_STATUS_LINK_LBN 2
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#define C22EXT_STATUS_LINK_WIDTH 1
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#define C22EXT_MSTSLV_CTRL 49161
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#define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
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#define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
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#define C22EXT_MSTSLV_STATUS 49162
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#define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
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#define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
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/* Time to wait between powering down the LNPGA and turning off the power
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* rails */
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#define LNPGA_PDOWN_WAIT (HZ / 5)
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struct tenxpress_phy_data {
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enum efx_loopback_mode loopback_mode;
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enum efx_phy_mode phy_mode;
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int bad_lp_tries;
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};
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static int tenxpress_init(struct efx_nic *efx)
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{
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/* Enable 312.5 MHz clock */
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efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
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1 << CLK312_EN_LBN);
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/* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
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efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
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1 << PMA_PMA_LED_ACTIVITY_LBN, true);
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efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
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SFX7101_PMA_PMD_LED_DEFAULT);
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return 0;
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}
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static int tenxpress_phy_probe(struct efx_nic *efx)
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{
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struct tenxpress_phy_data *phy_data;
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/* Allocate phy private storage */
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phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
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if (!phy_data)
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return -ENOMEM;
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efx->phy_data = phy_data;
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phy_data->phy_mode = efx->phy_mode;
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efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS;
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efx->mdio.mode_support = MDIO_SUPPORTS_C45;
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efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
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efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg |
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ADVERTISED_10000baseT_Full);
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return 0;
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}
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static int tenxpress_phy_init(struct efx_nic *efx)
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{
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int rc;
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falcon_board(efx)->type->init_phy(efx);
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if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
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rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
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if (rc < 0)
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return rc;
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rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
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if (rc < 0)
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return rc;
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}
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rc = tenxpress_init(efx);
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if (rc < 0)
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return rc;
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/* Reinitialise flow control settings */
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efx_link_set_wanted_fc(efx, efx->wanted_fc);
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efx_mdio_an_reconfigure(efx);
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schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
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/* Let XGXS and SerDes out of reset */
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falcon_reset_xaui(efx);
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return 0;
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}
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/* Perform a "special software reset" on the PHY. The caller is
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* responsible for saving and restoring the PHY hardware registers
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* properly, and masking/unmasking LASI */
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static int tenxpress_special_reset(struct efx_nic *efx)
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{
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int rc, reg;
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/* The XGMAC clock is driven from the SFX7101 312MHz clock, so
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* a special software reset can glitch the XGMAC sufficiently for stats
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* requests to fail. */
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falcon_stop_nic_stats(efx);
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/* Initiate reset */
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reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
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reg |= (1 << PMA_PMD_EXT_SSR_LBN);
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efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
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mdelay(200);
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/* Wait for the blocks to come out of reset */
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rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
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if (rc < 0)
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goto out;
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/* Try and reconfigure the device */
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rc = tenxpress_init(efx);
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if (rc < 0)
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goto out;
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/* Wait for the XGXS state machine to churn */
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mdelay(10);
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out:
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falcon_start_nic_stats(efx);
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return rc;
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}
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static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
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{
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struct tenxpress_phy_data *pd = efx->phy_data;
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bool bad_lp;
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int reg;
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if (link_ok) {
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bad_lp = false;
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} else {
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/* Check that AN has started but not completed. */
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reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
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if (!(reg & MDIO_AN_STAT1_LPABLE))
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return; /* LP status is unknown */
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bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
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if (bad_lp)
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pd->bad_lp_tries++;
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}
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/* Nothing to do if all is well and was previously so. */
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if (!pd->bad_lp_tries)
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return;
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/* Use the RX (red) LED as an error indicator once we've seen AN
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* failure several times in a row, and also log a message. */
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if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
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reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
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PMA_PMD_LED_OVERR_REG);
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reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
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if (!bad_lp) {
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reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
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} else {
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reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
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netif_err(efx, link, efx->net_dev,
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"appears to be plugged into a port"
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" that is not 10GBASE-T capable. The PHY"
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" supports 10GBASE-T ONLY, so no link can"
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" be established\n");
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}
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efx_mdio_write(efx, MDIO_MMD_PMAPMD,
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PMA_PMD_LED_OVERR_REG, reg);
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pd->bad_lp_tries = bad_lp;
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}
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}
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static bool sfx7101_link_ok(struct efx_nic *efx)
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{
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return efx_mdio_links_ok(efx,
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MDIO_DEVS_PMAPMD |
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MDIO_DEVS_PCS |
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MDIO_DEVS_PHYXS);
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}
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static void tenxpress_ext_loopback(struct efx_nic *efx)
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{
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efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
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1 << LOOPBACK_NEAR_LBN,
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efx->loopback_mode == LOOPBACK_PHYXS);
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}
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static void tenxpress_low_power(struct efx_nic *efx)
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{
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efx_mdio_set_mmds_lpower(
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efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
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TENXPRESS_REQUIRED_DEVS);
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}
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static int tenxpress_phy_reconfigure(struct efx_nic *efx)
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{
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struct tenxpress_phy_data *phy_data = efx->phy_data;
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bool phy_mode_change, loop_reset;
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if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
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phy_data->phy_mode = efx->phy_mode;
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return 0;
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}
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phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
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phy_data->phy_mode != PHY_MODE_NORMAL);
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loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) ||
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LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
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if (loop_reset || phy_mode_change) {
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tenxpress_special_reset(efx);
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falcon_reset_xaui(efx);
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}
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tenxpress_low_power(efx);
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efx_mdio_transmit_disable(efx);
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efx_mdio_phy_reconfigure(efx);
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tenxpress_ext_loopback(efx);
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efx_mdio_an_reconfigure(efx);
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phy_data->loopback_mode = efx->loopback_mode;
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phy_data->phy_mode = efx->phy_mode;
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return 0;
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}
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static void
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tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd);
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/* Poll for link state changes */
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static bool tenxpress_phy_poll(struct efx_nic *efx)
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{
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struct efx_link_state old_state = efx->link_state;
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efx->link_state.up = sfx7101_link_ok(efx);
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efx->link_state.speed = 10000;
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efx->link_state.fd = true;
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efx->link_state.fc = efx_mdio_get_pause(efx);
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sfx7101_check_bad_lp(efx, efx->link_state.up);
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return !efx_link_state_equal(&efx->link_state, &old_state);
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}
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static void sfx7101_phy_fini(struct efx_nic *efx)
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{
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int reg;
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/* Power down the LNPGA */
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reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
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efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
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/* Waiting here ensures that the board fini, which can turn
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* off the power to the PHY, won't get run until the LNPGA
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* powerdown has been given long enough to complete. */
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schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
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}
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static void tenxpress_phy_remove(struct efx_nic *efx)
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{
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kfree(efx->phy_data);
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efx->phy_data = NULL;
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}
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/* Override the RX, TX and link LEDs */
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void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
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{
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int reg;
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switch (mode) {
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case EFX_LED_OFF:
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reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) |
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(PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
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(PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN);
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break;
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case EFX_LED_ON:
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reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) |
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(PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) |
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(PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN);
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break;
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default:
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reg = SFX7101_PMA_PMD_LED_DEFAULT;
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break;
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}
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efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
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}
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static const char *const sfx7101_test_names[] = {
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"bist"
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};
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static const char *sfx7101_test_name(struct efx_nic *efx, unsigned int index)
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{
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if (index < ARRAY_SIZE(sfx7101_test_names))
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return sfx7101_test_names[index];
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return NULL;
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}
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static int
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sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags)
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{
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int rc;
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if (!(flags & ETH_TEST_FL_OFFLINE))
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return 0;
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/* BIST is automatically run after a special software reset */
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rc = tenxpress_special_reset(efx);
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results[0] = rc ? -1 : 1;
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efx_mdio_an_reconfigure(efx);
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return rc;
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}
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static void
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tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
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{
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u32 adv = 0, lpa = 0;
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int reg;
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reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
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if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
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adv |= ADVERTISED_10000baseT_Full;
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reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
|
|
if (reg & MDIO_AN_10GBT_STAT_LP10G)
|
|
lpa |= ADVERTISED_10000baseT_Full;
|
|
|
|
mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa);
|
|
|
|
/* In loopback, the PHY automatically brings up the correct interface,
|
|
* but doesn't advertise the correct speed. So override it */
|
|
if (LOOPBACK_EXTERNAL(efx))
|
|
ecmd->speed = SPEED_10000;
|
|
}
|
|
|
|
static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
|
|
{
|
|
if (!ecmd->autoneg)
|
|
return -EINVAL;
|
|
|
|
return efx_mdio_set_settings(efx, ecmd);
|
|
}
|
|
|
|
static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising)
|
|
{
|
|
efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
|
|
MDIO_AN_10GBT_CTRL_ADV10G,
|
|
advertising & ADVERTISED_10000baseT_Full);
|
|
}
|
|
|
|
struct efx_phy_operations falcon_sfx7101_phy_ops = {
|
|
.probe = tenxpress_phy_probe,
|
|
.init = tenxpress_phy_init,
|
|
.reconfigure = tenxpress_phy_reconfigure,
|
|
.poll = tenxpress_phy_poll,
|
|
.fini = sfx7101_phy_fini,
|
|
.remove = tenxpress_phy_remove,
|
|
.get_settings = tenxpress_get_settings,
|
|
.set_settings = tenxpress_set_settings,
|
|
.set_npage_adv = sfx7101_set_npage_adv,
|
|
.test_alive = efx_mdio_test_alive,
|
|
.test_name = sfx7101_test_name,
|
|
.run_tests = sfx7101_run_tests,
|
|
};
|