327 lines
12 KiB
C
327 lines
12 KiB
C
/*
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* Motion Eye video4linux driver for Sony Vaio PictureBook
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*
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* Copyright (C) 2001-2004 Stelian Pop <stelian@popies.net>
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*
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* Copyright (C) 2001-2002 Alcôve <www.alcove.com>
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*
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* Copyright (C) 2000 Andrew Tridgell <tridge@valinux.com>
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*
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* Earlier work by Werner Almesberger, Paul `Rusty' Russell and Paul Mackerras.
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*
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* Some parts borrowed from various video4linux drivers, especially
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* bttv-driver.c and zoran.c, see original files for credits.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _MEYE_PRIV_H_
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#define _MEYE_PRIV_H_
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#define MEYE_DRIVER_MAJORVERSION 1
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#define MEYE_DRIVER_MINORVERSION 14
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#define MEYE_DRIVER_VERSION __stringify(MEYE_DRIVER_MAJORVERSION) "." \
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__stringify(MEYE_DRIVER_MINORVERSION)
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kfifo.h>
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#include <media/v4l2-ctrls.h>
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/****************************************************************************/
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/* Motion JPEG chip registers */
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/****************************************************************************/
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/* Motion JPEG chip PCI configuration registers */
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#define MCHIP_PCI_POWER_CSR 0x54
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#define MCHIP_PCI_MCORE_STATUS 0x60 /* see HIC_STATUS */
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#define MCHIP_PCI_HOSTUSEREQ_SET 0x64
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#define MCHIP_PCI_HOSTUSEREQ_CLR 0x68
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#define MCHIP_PCI_LOWPOWER_SET 0x6c
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#define MCHIP_PCI_LOWPOWER_CLR 0x70
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#define MCHIP_PCI_SOFTRESET_SET 0x74
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/* Motion JPEG chip memory mapped registers */
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#define MCHIP_MM_REGS 0x200 /* 512 bytes */
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#define MCHIP_REG_TIMEOUT 1000 /* reg access, ~us */
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#define MCHIP_MCC_VRJ_TIMEOUT 1000 /* MCC & VRJ access */
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#define MCHIP_MM_PCI_MODE 0x00 /* PCI access mode */
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#define MCHIP_MM_PCI_MODE_RETRY 0x00000001 /* retry mode */
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#define MCHIP_MM_PCI_MODE_MASTER 0x00000002 /* master access */
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#define MCHIP_MM_PCI_MODE_READ_LINE 0x00000004 /* read line */
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#define MCHIP_MM_INTA 0x04 /* Int status/mask */
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#define MCHIP_MM_INTA_MCC 0x00000001 /* MCC interrupt */
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#define MCHIP_MM_INTA_VRJ 0x00000002 /* VRJ interrupt */
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#define MCHIP_MM_INTA_HIC_1 0x00000004 /* one frame done */
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#define MCHIP_MM_INTA_HIC_1_MASK 0x00000400 /* 1: enable */
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#define MCHIP_MM_INTA_HIC_END 0x00000008 /* all frames done */
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#define MCHIP_MM_INTA_HIC_END_MASK 0x00000800
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#define MCHIP_MM_INTA_JPEG 0x00000010 /* decompress. error */
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#define MCHIP_MM_INTA_JPEG_MASK 0x00001000
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#define MCHIP_MM_INTA_CAPTURE 0x00000020 /* capture end */
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#define MCHIP_MM_INTA_PCI_ERR 0x00000040 /* PCI error */
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#define MCHIP_MM_INTA_PCI_ERR_MASK 0x00004000
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#define MCHIP_MM_PT_ADDR 0x08 /* page table address*/
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/* n*4kB */
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#define MCHIP_NB_PAGES 1024 /* pages for display */
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#define MCHIP_NB_PAGES_MJPEG 256 /* pages for mjpeg */
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#define MCHIP_MM_FIR(n) (0x0c+(n)*4) /* Frame info 0-3 */
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#define MCHIP_MM_FIR_RDY 0x00000001 /* frame ready */
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#define MCHIP_MM_FIR_FAILFR_MASK 0xf8000000 /* # of failed frames */
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#define MCHIP_MM_FIR_FAILFR_SHIFT 27
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/* continuous comp/decomp mode */
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#define MCHIP_MM_FIR_C_ENDL_MASK 0x000007fe /* end DW [10] */
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#define MCHIP_MM_FIR_C_ENDL_SHIFT 1
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#define MCHIP_MM_FIR_C_ENDP_MASK 0x0007f800 /* end page [8] */
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#define MCHIP_MM_FIR_C_ENDP_SHIFT 11
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#define MCHIP_MM_FIR_C_STARTP_MASK 0x07f80000 /* start page [8] */
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#define MCHIP_MM_FIR_C_STARTP_SHIFT 19
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/* continuous picture output mode */
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#define MCHIP_MM_FIR_O_STARTP_MASK 0x7ffe0000 /* start page [10] */
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#define MCHIP_MM_FIR_O_STARTP_SHIFT 17
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#define MCHIP_MM_FIFO_DATA 0x1c /* PCI TGT FIFO data */
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#define MCHIP_MM_FIFO_STATUS 0x20 /* PCI TGT FIFO stat */
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#define MCHIP_MM_FIFO_MASK 0x00000003
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#define MCHIP_MM_FIFO_WAIT_OR_READY 0x00000002 /* Bits common to WAIT & READY*/
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#define MCHIP_MM_FIFO_IDLE 0x0 /* HIC idle */
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#define MCHIP_MM_FIFO_IDLE1 0x1 /* idem ??? */
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#define MCHIP_MM_FIFO_WAIT 0x2 /* wait request */
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#define MCHIP_MM_FIFO_READY 0x3 /* data ready */
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#define MCHIP_HIC_HOST_USEREQ 0x40 /* host uses MCORE */
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#define MCHIP_HIC_TP_BUSY 0x44 /* taking picture */
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#define MCHIP_HIC_PIC_SAVED 0x48 /* pic in SDRAM */
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#define MCHIP_HIC_LOWPOWER 0x4c /* clock stopped */
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#define MCHIP_HIC_CTL 0x50 /* HIC control */
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#define MCHIP_HIC_CTL_SOFT_RESET 0x00000001 /* MCORE reset */
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#define MCHIP_HIC_CTL_MCORE_RDY 0x00000002 /* MCORE ready */
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#define MCHIP_HIC_CMD 0x54 /* HIC command */
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#define MCHIP_HIC_CMD_BITS 0x00000003 /* cmd width=[1:0]*/
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#define MCHIP_HIC_CMD_NOOP 0x0
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#define MCHIP_HIC_CMD_START 0x1
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#define MCHIP_HIC_CMD_STOP 0x2
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#define MCHIP_HIC_MODE 0x58
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#define MCHIP_HIC_MODE_NOOP 0x0
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#define MCHIP_HIC_MODE_STILL_CAP 0x1 /* still pic capt */
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#define MCHIP_HIC_MODE_DISPLAY 0x2 /* display */
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#define MCHIP_HIC_MODE_STILL_COMP 0x3 /* still pic comp. */
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#define MCHIP_HIC_MODE_STILL_DECOMP 0x4 /* still pic decomp. */
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#define MCHIP_HIC_MODE_CONT_COMP 0x5 /* cont capt+comp */
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#define MCHIP_HIC_MODE_CONT_DECOMP 0x6 /* cont decomp+disp */
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#define MCHIP_HIC_MODE_STILL_OUT 0x7 /* still pic output */
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#define MCHIP_HIC_MODE_CONT_OUT 0x8 /* cont output */
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#define MCHIP_HIC_STATUS 0x5c
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#define MCHIP_HIC_STATUS_MCC_RDY 0x00000001 /* MCC reg acc ok */
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#define MCHIP_HIC_STATUS_VRJ_RDY 0x00000002 /* VRJ reg acc ok */
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#define MCHIP_HIC_STATUS_IDLE 0x00000003
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#define MCHIP_HIC_STATUS_CAPDIS 0x00000004 /* cap/disp in prog */
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#define MCHIP_HIC_STATUS_COMPDEC 0x00000008 /* (de)comp in prog */
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#define MCHIP_HIC_STATUS_BUSY 0x00000010 /* HIC busy */
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#define MCHIP_HIC_S_RATE 0x60 /* MJPEG # frames */
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#define MCHIP_HIC_PCI_VFMT 0x64 /* video format */
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#define MCHIP_HIC_PCI_VFMT_YVYU 0x00000001 /* 0: V Y' U Y */
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/* 1: Y' V Y U */
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#define MCHIP_MCC_CMD 0x80 /* MCC commands */
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#define MCHIP_MCC_CMD_INITIAL 0x0 /* idle ? */
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#define MCHIP_MCC_CMD_IIC_START_SET 0x1
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#define MCHIP_MCC_CMD_IIC_END_SET 0x2
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#define MCHIP_MCC_CMD_FM_WRITE 0x3 /* frame memory */
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#define MCHIP_MCC_CMD_FM_READ 0x4
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#define MCHIP_MCC_CMD_FM_STOP 0x5
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#define MCHIP_MCC_CMD_CAPTURE 0x6
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#define MCHIP_MCC_CMD_DISPLAY 0x7
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#define MCHIP_MCC_CMD_END_DISP 0x8
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#define MCHIP_MCC_CMD_STILL_COMP 0x9
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#define MCHIP_MCC_CMD_STILL_DECOMP 0xa
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#define MCHIP_MCC_CMD_STILL_OUTPUT 0xb
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#define MCHIP_MCC_CMD_CONT_OUTPUT 0xc
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#define MCHIP_MCC_CMD_CONT_COMP 0xd
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#define MCHIP_MCC_CMD_CONT_DECOMP 0xe
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#define MCHIP_MCC_CMD_RESET 0xf /* MCC reset */
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#define MCHIP_MCC_IIC_WR 0x84
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#define MCHIP_MCC_MCC_WR 0x88
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#define MCHIP_MCC_MCC_RD 0x8c
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#define MCHIP_MCC_STATUS 0x90
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#define MCHIP_MCC_STATUS_CAPT 0x00000001 /* capturing */
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#define MCHIP_MCC_STATUS_DISP 0x00000002 /* displaying */
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#define MCHIP_MCC_STATUS_COMP 0x00000004 /* compressing */
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#define MCHIP_MCC_STATUS_DECOMP 0x00000008 /* decompressing */
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#define MCHIP_MCC_STATUS_MCC_WR 0x00000010 /* register ready */
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#define MCHIP_MCC_STATUS_MCC_RD 0x00000020 /* register ready */
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#define MCHIP_MCC_STATUS_IIC_WR 0x00000040 /* register ready */
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#define MCHIP_MCC_STATUS_OUTPUT 0x00000080 /* output in prog */
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#define MCHIP_MCC_SIG_POLARITY 0x94
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#define MCHIP_MCC_SIG_POL_VS_H 0x00000001 /* VS active-high */
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#define MCHIP_MCC_SIG_POL_HS_H 0x00000002 /* HS active-high */
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#define MCHIP_MCC_SIG_POL_DOE_H 0x00000004 /* DOE active-high */
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#define MCHIP_MCC_IRQ 0x98
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#define MCHIP_MCC_IRQ_CAPDIS_STRT 0x00000001 /* cap/disp started */
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#define MCHIP_MCC_IRQ_CAPDIS_STRT_MASK 0x00000010
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#define MCHIP_MCC_IRQ_CAPDIS_END 0x00000002 /* cap/disp ended */
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#define MCHIP_MCC_IRQ_CAPDIS_END_MASK 0x00000020
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#define MCHIP_MCC_IRQ_COMPDEC_STRT 0x00000004 /* (de)comp started */
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#define MCHIP_MCC_IRQ_COMPDEC_STRT_MASK 0x00000040
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#define MCHIP_MCC_IRQ_COMPDEC_END 0x00000008 /* (de)comp ended */
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#define MCHIP_MCC_IRQ_COMPDEC_END_MASK 0x00000080
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#define MCHIP_MCC_HSTART 0x9c /* video in */
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#define MCHIP_MCC_VSTART 0xa0
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#define MCHIP_MCC_HCOUNT 0xa4
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#define MCHIP_MCC_VCOUNT 0xa8
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#define MCHIP_MCC_R_XBASE 0xac /* capt/disp */
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#define MCHIP_MCC_R_YBASE 0xb0
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#define MCHIP_MCC_R_XRANGE 0xb4
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#define MCHIP_MCC_R_YRANGE 0xb8
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#define MCHIP_MCC_B_XBASE 0xbc /* comp/decomp */
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#define MCHIP_MCC_B_YBASE 0xc0
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#define MCHIP_MCC_B_XRANGE 0xc4
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#define MCHIP_MCC_B_YRANGE 0xc8
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#define MCHIP_MCC_R_SAMPLING 0xcc /* 1: 1:4 */
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#define MCHIP_VRJ_CMD 0x100 /* VRJ commands */
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/* VRJ registers (see table 12.2.4) */
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#define MCHIP_VRJ_COMPRESSED_DATA 0x1b0
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#define MCHIP_VRJ_PIXEL_DATA 0x1b8
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#define MCHIP_VRJ_BUS_MODE 0x100
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#define MCHIP_VRJ_SIGNAL_ACTIVE_LEVEL 0x108
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#define MCHIP_VRJ_PDAT_USE 0x110
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#define MCHIP_VRJ_MODE_SPECIFY 0x118
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#define MCHIP_VRJ_LIMIT_COMPRESSED_LO 0x120
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#define MCHIP_VRJ_LIMIT_COMPRESSED_HI 0x124
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#define MCHIP_VRJ_COMP_DATA_FORMAT 0x128
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#define MCHIP_VRJ_TABLE_DATA 0x140
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#define MCHIP_VRJ_RESTART_INTERVAL 0x148
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#define MCHIP_VRJ_NUM_LINES 0x150
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#define MCHIP_VRJ_NUM_PIXELS 0x158
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#define MCHIP_VRJ_NUM_COMPONENTS 0x160
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#define MCHIP_VRJ_SOF1 0x168
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#define MCHIP_VRJ_SOF2 0x170
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#define MCHIP_VRJ_SOF3 0x178
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#define MCHIP_VRJ_SOF4 0x180
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#define MCHIP_VRJ_SOS 0x188
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#define MCHIP_VRJ_SOFT_RESET 0x190
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#define MCHIP_VRJ_STATUS 0x1c0
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#define MCHIP_VRJ_STATUS_BUSY 0x00001
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#define MCHIP_VRJ_STATUS_COMP_ACCESS 0x00002
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#define MCHIP_VRJ_STATUS_PIXEL_ACCESS 0x00004
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#define MCHIP_VRJ_STATUS_ERROR 0x00008
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#define MCHIP_VRJ_IRQ_FLAG 0x1c8
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#define MCHIP_VRJ_ERROR_REPORT 0x1d8
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#define MCHIP_VRJ_START_COMMAND 0x1a0
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/****************************************************************************/
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/* Driver definitions. */
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/****************************************************************************/
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/* Sony Programmable I/O Controller for accessing the camera commands */
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#include <linux/sony-laptop.h>
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/* private API definitions */
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#include <linux/meye.h>
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#include <linux/mutex.h>
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/* Enable jpg software correction */
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#define MEYE_JPEG_CORRECTION 1
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/* Maximum size of a buffer */
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#define MEYE_MAX_BUFSIZE 614400 /* 640 * 480 * 2 */
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/* Maximum number of buffers */
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#define MEYE_MAX_BUFNBRS 32
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/* State of a buffer */
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#define MEYE_BUF_UNUSED 0 /* not used */
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#define MEYE_BUF_USING 1 /* currently grabbing / playing */
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#define MEYE_BUF_DONE 2 /* done */
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/* grab buffer */
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struct meye_grab_buffer {
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int state; /* state of buffer */
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unsigned long size; /* size of jpg frame */
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struct timeval timestamp; /* timestamp */
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unsigned long sequence; /* sequence number */
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};
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/* size of kfifos containings buffer indices */
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#define MEYE_QUEUE_SIZE MEYE_MAX_BUFNBRS
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/* Motion Eye device structure */
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struct meye {
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struct v4l2_device v4l2_dev; /* Main v4l2_device struct */
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struct v4l2_ctrl_handler hdl;
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struct pci_dev *mchip_dev; /* pci device */
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u8 mchip_irq; /* irq */
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u8 mchip_mode; /* actual mchip mode: HIC_MODE... */
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u8 mchip_fnum; /* current mchip frame number */
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unsigned char __iomem *mchip_mmregs;/* mchip: memory mapped registers */
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u8 *mchip_ptable[MCHIP_NB_PAGES];/* mchip: ptable */
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void *mchip_ptable_toc; /* mchip: ptable toc */
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dma_addr_t mchip_dmahandle; /* mchip: dma handle to ptable toc */
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unsigned char *grab_fbuffer; /* capture framebuffer */
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unsigned char *grab_temp; /* temporary buffer */
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/* list of buffers */
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struct meye_grab_buffer grab_buffer[MEYE_MAX_BUFNBRS];
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int vma_use_count[MEYE_MAX_BUFNBRS]; /* mmap count */
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struct mutex lock; /* mutex for open/mmap... */
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struct kfifo grabq; /* queue for buffers to be grabbed */
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spinlock_t grabq_lock; /* lock protecting the queue */
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struct kfifo doneq; /* queue for grabbed buffers */
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spinlock_t doneq_lock; /* lock protecting the queue */
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wait_queue_head_t proc_list; /* wait queue */
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struct video_device *vdev; /* video device parameters */
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u16 brightness;
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u16 hue;
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u16 contrast;
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u16 colour;
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struct meye_params params; /* additional parameters */
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unsigned long in_use; /* set to 1 if the device is in use */
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#ifdef CONFIG_PM
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u8 pm_mchip_mode; /* old mchip mode */
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#endif
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};
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#endif
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