317 lines
8.1 KiB
C
317 lines
8.1 KiB
C
/*
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* Suspend support specific for i386.
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*
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* Distribute under GPLv2
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*
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* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
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* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
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*/
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#include <linux/smp.h>
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#include <linux/suspend.h>
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#include <asm/proto.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/mtrr.h>
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/* References to section boundaries */
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extern const void __nosave_begin, __nosave_end;
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static void fix_processor_context(void);
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struct saved_context saved_context;
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/**
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* __save_processor_state - save CPU registers before creating a
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* hibernation image and before restoring the memory state from it
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* @ctxt - structure to store the registers contents in
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*
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* NOTE: If there is a CPU register the modification of which by the
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* boot kernel (ie. the kernel used for loading the hibernation image)
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* might affect the operations of the restored target kernel (ie. the one
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* saved in the hibernation image), then its contents must be saved by this
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* function. In other words, if kernel A is hibernated and different
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* kernel B is used for loading the hibernation image into memory, the
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* kernel A's __save_processor_state() function must save all registers
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* needed by kernel A, so that it can operate correctly after the resume
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* regardless of what kernel B does in the meantime.
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*/
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static void __save_processor_state(struct saved_context *ctxt)
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{
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kernel_fpu_begin();
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/*
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* descriptor tables
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*/
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store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
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store_idt((struct desc_ptr *)&ctxt->idt_limit);
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store_tr(ctxt->tr);
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/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
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/*
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* segment registers
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*/
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asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
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asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
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asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
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asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
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asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
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rdmsrl(MSR_FS_BASE, ctxt->fs_base);
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rdmsrl(MSR_GS_BASE, ctxt->gs_base);
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rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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mtrr_save_fixed_ranges(NULL);
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/*
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* control registers
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*/
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rdmsrl(MSR_EFER, ctxt->efer);
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ctxt->cr0 = read_cr0();
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ctxt->cr2 = read_cr2();
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ctxt->cr3 = read_cr3();
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ctxt->cr4 = read_cr4();
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ctxt->cr8 = read_cr8();
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}
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void save_processor_state(void)
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{
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__save_processor_state(&saved_context);
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}
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static void do_fpu_end(void)
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{
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/*
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* Restore FPU regs if necessary
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*/
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kernel_fpu_end();
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}
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/**
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* __restore_processor_state - restore the contents of CPU registers saved
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* by __save_processor_state()
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* @ctxt - structure to load the registers contents from
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*/
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static void __restore_processor_state(struct saved_context *ctxt)
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{
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/*
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* control registers
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*/
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wrmsrl(MSR_EFER, ctxt->efer);
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write_cr8(ctxt->cr8);
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write_cr4(ctxt->cr4);
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write_cr3(ctxt->cr3);
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write_cr2(ctxt->cr2);
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write_cr0(ctxt->cr0);
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/*
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* now restore the descriptor tables to their proper values
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* ltr is done i fix_processor_context().
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*/
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load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
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load_idt((const struct desc_ptr *)&ctxt->idt_limit);
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/*
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* segment registers
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*/
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asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
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asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
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asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
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load_gs_index(ctxt->gs);
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asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
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wrmsrl(MSR_FS_BASE, ctxt->fs_base);
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wrmsrl(MSR_GS_BASE, ctxt->gs_base);
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wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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fix_processor_context();
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do_fpu_end();
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mtrr_ap_init();
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}
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void restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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}
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static void fix_processor_context(void)
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{
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int cpu = smp_processor_id();
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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set_tss_desc(cpu,t); /* This just modifies memory; should not be necessary. But... This is necessary, because 386 hardware has concept of busy TSS or some similar stupidity. */
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get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
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syscall_init(); /* This sets MSR_*STAR and related */
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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/*
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* Now maybe reload the debug registers
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*/
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if (current->thread.debugreg7){
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loaddebug(¤t->thread, 0);
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loaddebug(¤t->thread, 1);
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loaddebug(¤t->thread, 2);
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loaddebug(¤t->thread, 3);
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/* no 4 and 5 */
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loaddebug(¤t->thread, 6);
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loaddebug(¤t->thread, 7);
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}
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}
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#ifdef CONFIG_HIBERNATION
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/* Defined in arch/x86_64/kernel/suspend_asm.S */
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extern int restore_image(void);
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/*
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* Address to jump to in the last phase of restore in order to get to the image
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* kernel's text (this value is passed in the image header).
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*/
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unsigned long restore_jump_address;
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/*
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* Value of the cr3 register from before the hibernation (this value is passed
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* in the image header).
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*/
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unsigned long restore_cr3;
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pgd_t *temp_level4_pgt;
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void *relocated_restore_code;
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static int res_phys_pud_init(pud_t *pud, unsigned long address, unsigned long end)
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{
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long i, j;
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i = pud_index(address);
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pud = pud + i;
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for (; i < PTRS_PER_PUD; pud++, i++) {
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unsigned long paddr;
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pmd_t *pmd;
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paddr = address + i*PUD_SIZE;
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if (paddr >= end)
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break;
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pmd = (pmd_t *)get_safe_page(GFP_ATOMIC);
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if (!pmd)
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return -ENOMEM;
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set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
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for (j = 0; j < PTRS_PER_PMD; pmd++, j++, paddr += PMD_SIZE) {
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unsigned long pe;
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if (paddr >= end)
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break;
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pe = __PAGE_KERNEL_LARGE_EXEC | paddr;
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pe &= __supported_pte_mask;
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set_pmd(pmd, __pmd(pe));
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}
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}
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return 0;
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}
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static int set_up_temporary_mappings(void)
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{
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unsigned long start, end, next;
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int error;
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temp_level4_pgt = (pgd_t *)get_safe_page(GFP_ATOMIC);
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if (!temp_level4_pgt)
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return -ENOMEM;
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/* It is safe to reuse the original kernel mapping */
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set_pgd(temp_level4_pgt + pgd_index(__START_KERNEL_map),
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init_level4_pgt[pgd_index(__START_KERNEL_map)]);
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/* Set up the direct mapping from scratch */
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start = (unsigned long)pfn_to_kaddr(0);
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end = (unsigned long)pfn_to_kaddr(end_pfn);
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for (; start < end; start = next) {
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pud_t *pud = (pud_t *)get_safe_page(GFP_ATOMIC);
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if (!pud)
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return -ENOMEM;
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next = start + PGDIR_SIZE;
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if (next > end)
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next = end;
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if ((error = res_phys_pud_init(pud, __pa(start), __pa(next))))
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return error;
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set_pgd(temp_level4_pgt + pgd_index(start),
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mk_kernel_pgd(__pa(pud)));
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}
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return 0;
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}
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int swsusp_arch_resume(void)
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{
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int error;
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/* We have got enough memory and from now on we cannot recover */
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if ((error = set_up_temporary_mappings()))
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return error;
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relocated_restore_code = (void *)get_safe_page(GFP_ATOMIC);
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if (!relocated_restore_code)
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return -ENOMEM;
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memcpy(relocated_restore_code, &core_restore_code,
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&restore_registers - &core_restore_code);
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restore_image();
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return 0;
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}
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/*
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* pfn_is_nosave - check if given pfn is in the 'nosave' section
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*/
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int pfn_is_nosave(unsigned long pfn)
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{
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unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
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unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
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return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
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}
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struct restore_data_record {
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unsigned long jump_address;
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unsigned long cr3;
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unsigned long magic;
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};
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#define RESTORE_MAGIC 0x0123456789ABCDEFUL
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/**
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* arch_hibernation_header_save - populate the architecture specific part
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* of a hibernation image header
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* @addr: address to save the data at
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*/
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int arch_hibernation_header_save(void *addr, unsigned int max_size)
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{
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struct restore_data_record *rdr = addr;
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if (max_size < sizeof(struct restore_data_record))
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return -EOVERFLOW;
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rdr->jump_address = restore_jump_address;
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rdr->cr3 = restore_cr3;
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rdr->magic = RESTORE_MAGIC;
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return 0;
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}
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/**
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* arch_hibernation_header_restore - read the architecture specific data
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* from the hibernation image header
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* @addr: address to read the data from
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*/
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int arch_hibernation_header_restore(void *addr)
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{
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struct restore_data_record *rdr = addr;
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restore_jump_address = rdr->jump_address;
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restore_cr3 = rdr->cr3;
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return (rdr->magic == RESTORE_MAGIC) ? 0 : -EINVAL;
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}
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#endif /* CONFIG_HIBERNATION */
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