370 lines
11 KiB
C
370 lines
11 KiB
C
#ifndef DRIVERS_PCI_H
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#define DRIVERS_PCI_H
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#define PCI_FIND_CAP_TTL 48
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#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
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extern const unsigned char pcie_link_speed[];
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bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
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/* Functions internal to the PCI core code */
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int pci_create_sysfs_dev_files(struct pci_dev *pdev);
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void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
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#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
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static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
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{ return; }
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static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
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{ return; }
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#else
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void pci_create_firmware_label_files(struct pci_dev *pdev);
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void pci_remove_firmware_label_files(struct pci_dev *pdev);
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#endif
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void pci_cleanup_rom(struct pci_dev *dev);
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enum pci_mmap_api {
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PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
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PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
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};
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int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
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enum pci_mmap_api mmap_api);
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int pci_probe_reset_function(struct pci_dev *dev);
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/**
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* struct pci_platform_pm_ops - Firmware PM callbacks
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*
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* @is_manageable: returns 'true' if given device is power manageable by the
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* platform firmware
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*
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* @set_state: invokes the platform firmware to set the device's power state
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*
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* @get_state: queries the platform firmware for a device's current power state
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*
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* @choose_state: returns PCI power state of given device preferred by the
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* platform; to be used during system-wide transitions from a
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* sleeping state to the working state and vice versa
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*
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* @set_wakeup: enables/disables wakeup capability for the device
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*
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* @need_resume: returns 'true' if the given device (which is currently
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* suspended) needs to be resumed to be configured for system
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* wakeup.
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*
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* If given platform is generally capable of power managing PCI devices, all of
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* these callbacks are mandatory.
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*/
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struct pci_platform_pm_ops {
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bool (*is_manageable)(struct pci_dev *dev);
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int (*set_state)(struct pci_dev *dev, pci_power_t state);
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pci_power_t (*get_state)(struct pci_dev *dev);
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pci_power_t (*choose_state)(struct pci_dev *dev);
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int (*set_wakeup)(struct pci_dev *dev, bool enable);
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bool (*need_resume)(struct pci_dev *dev);
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};
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int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
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void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
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void pci_power_up(struct pci_dev *dev);
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void pci_disable_enabled_device(struct pci_dev *dev);
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int pci_finish_runtime_suspend(struct pci_dev *dev);
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int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
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void pci_pme_restore(struct pci_dev *dev);
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bool pci_dev_keep_suspended(struct pci_dev *dev);
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void pci_dev_complete_resume(struct pci_dev *pci_dev);
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void pci_config_pm_runtime_get(struct pci_dev *dev);
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void pci_config_pm_runtime_put(struct pci_dev *dev);
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void pci_pm_init(struct pci_dev *dev);
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void pci_ea_init(struct pci_dev *dev);
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void pci_allocate_cap_save_buffers(struct pci_dev *dev);
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void pci_free_cap_save_buffers(struct pci_dev *dev);
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bool pci_bridge_d3_possible(struct pci_dev *dev);
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void pci_bridge_d3_update(struct pci_dev *dev);
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static inline void pci_wakeup_event(struct pci_dev *dev)
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{
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/* Wait 100 ms before the system can be put into a sleep state. */
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pm_wakeup_event(&dev->dev, 100);
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}
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static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
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{
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return !!(pci_dev->subordinate);
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}
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static inline bool pci_power_manageable(struct pci_dev *pci_dev)
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{
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/*
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* Currently we allow normal PCI devices and PCI bridges transition
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* into D3 if their bridge_d3 is set.
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*/
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return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
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}
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struct pci_vpd_ops {
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ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
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ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
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int (*set_size)(struct pci_dev *dev, size_t len);
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};
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struct pci_vpd {
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const struct pci_vpd_ops *ops;
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struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
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struct mutex lock;
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unsigned int len;
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u16 flag;
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u8 cap;
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u8 busy:1;
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u8 valid:1;
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};
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int pci_vpd_init(struct pci_dev *dev);
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void pci_vpd_release(struct pci_dev *dev);
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/* PCI /proc functions */
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#ifdef CONFIG_PROC_FS
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int pci_proc_attach_device(struct pci_dev *dev);
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int pci_proc_detach_device(struct pci_dev *dev);
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int pci_proc_detach_bus(struct pci_bus *bus);
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#else
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static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
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#endif
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/* Functions for PCI Hotplug drivers to use */
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int pci_hp_add_bridge(struct pci_dev *dev);
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#ifdef HAVE_PCI_LEGACY
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void pci_create_legacy_files(struct pci_bus *bus);
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void pci_remove_legacy_files(struct pci_bus *bus);
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#else
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static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
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static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
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#endif
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/* Lock for read/write access to pci device and bus lists */
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extern struct rw_semaphore pci_bus_sem;
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extern raw_spinlock_t pci_lock;
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extern unsigned int pci_pm_d3_delay;
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#ifdef CONFIG_PCI_MSI
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void pci_no_msi(void);
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#else
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static inline void pci_no_msi(void) { }
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#endif
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static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
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{
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u16 control;
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pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
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control &= ~PCI_MSI_FLAGS_ENABLE;
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if (enable)
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control |= PCI_MSI_FLAGS_ENABLE;
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pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
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}
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static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
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{
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u16 ctrl;
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pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
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ctrl &= ~clear;
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ctrl |= set;
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pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
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}
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void pci_realloc_get_opt(char *);
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static inline int pci_no_d1d2(struct pci_dev *dev)
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{
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unsigned int parent_dstates = 0;
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if (dev->bus->self)
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parent_dstates = dev->bus->self->no_d1d2;
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return (dev->no_d1d2 || parent_dstates);
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}
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extern const struct attribute_group *pci_dev_groups[];
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extern const struct attribute_group *pcibus_groups[];
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extern struct device_type pci_dev_type;
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extern const struct attribute_group *pci_bus_groups[];
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/**
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* pci_match_one_device - Tell if a PCI device structure has a matching
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* PCI device id structure
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* @id: single PCI device id structure to match
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* @dev: the PCI device structure to match against
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*
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* Returns the matching pci_device_id structure or %NULL if there is no match.
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*/
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static inline const struct pci_device_id *
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pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
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{
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if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
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(id->device == PCI_ANY_ID || id->device == dev->device) &&
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(id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
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(id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
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!((id->class ^ dev->class) & id->class_mask))
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return id;
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return NULL;
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}
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/* PCI slot sysfs helper code */
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#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
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extern struct kset *pci_slots_kset;
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struct pci_slot_attribute {
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struct attribute attr;
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ssize_t (*show)(struct pci_slot *, char *);
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ssize_t (*store)(struct pci_slot *, const char *, size_t);
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};
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#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
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enum pci_bar_type {
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pci_bar_unknown, /* Standard PCI BAR probe */
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pci_bar_io, /* An io port BAR */
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pci_bar_mem32, /* A 32-bit memory BAR */
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pci_bar_mem64, /* A 64-bit memory BAR */
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};
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int crs_timeout);
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int pci_setup_device(struct pci_dev *dev);
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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struct resource *res, unsigned int reg);
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void pci_configure_ari(struct pci_dev *dev);
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void __pci_bus_size_bridges(struct pci_bus *bus,
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struct list_head *realloc_head);
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void __pci_bus_assign_resources(const struct pci_bus *bus,
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struct list_head *realloc_head,
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struct list_head *fail_head);
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bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
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void pci_reassigndev_resource_alignment(struct pci_dev *dev);
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void pci_disable_bridge_window(struct pci_dev *dev);
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/* Single Root I/O Virtualization */
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struct pci_sriov {
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int pos; /* capability position */
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int nres; /* number of resources */
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u32 cap; /* SR-IOV Capabilities */
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u16 ctrl; /* SR-IOV Control */
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u16 total_VFs; /* total VFs associated with the PF */
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u16 initial_VFs; /* initial VFs associated with the PF */
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u16 num_VFs; /* number of VFs available */
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u16 offset; /* first VF Routing ID offset */
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u16 stride; /* following VF stride */
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u32 pgsz; /* page size for BAR alignment */
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u8 link; /* Function Dependency Link */
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u8 max_VF_buses; /* max buses consumed by VFs */
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u16 driver_max_VFs; /* max num VFs driver supports */
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struct pci_dev *dev; /* lowest numbered PF */
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struct pci_dev *self; /* this PF */
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resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
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bool drivers_autoprobe; /* auto probing of VFs by driver */
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};
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/* pci_dev priv_flags */
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#define PCI_DEV_DISCONNECTED 0
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static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
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{
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set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
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return 0;
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}
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static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
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{
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return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
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}
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#ifdef CONFIG_PCI_ATS
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void pci_restore_ats_state(struct pci_dev *dev);
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#else
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static inline void pci_restore_ats_state(struct pci_dev *dev)
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{
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}
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#endif /* CONFIG_PCI_ATS */
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#ifdef CONFIG_PCI_IOV
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int pci_iov_init(struct pci_dev *dev);
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void pci_iov_release(struct pci_dev *dev);
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void pci_iov_update_resource(struct pci_dev *dev, int resno);
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resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
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void pci_restore_iov_state(struct pci_dev *dev);
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int pci_iov_bus_range(struct pci_bus *bus);
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#else
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static inline int pci_iov_init(struct pci_dev *dev)
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{
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return -ENODEV;
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}
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static inline void pci_iov_release(struct pci_dev *dev)
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{
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}
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static inline void pci_restore_iov_state(struct pci_dev *dev)
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{
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}
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static inline int pci_iov_bus_range(struct pci_bus *bus)
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{
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return 0;
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}
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#endif /* CONFIG_PCI_IOV */
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unsigned long pci_cardbus_resource_alignment(struct resource *);
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static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
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struct resource *res)
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{
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#ifdef CONFIG_PCI_IOV
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int resno = res - dev->resource;
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if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
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return pci_sriov_resource_alignment(dev, resno);
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#endif
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if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
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return pci_cardbus_resource_alignment(res);
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return resource_alignment(res);
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}
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void pci_enable_acs(struct pci_dev *dev);
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#ifdef CONFIG_PCIE_PTM
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void pci_ptm_init(struct pci_dev *dev);
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#else
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static inline void pci_ptm_init(struct pci_dev *dev) { }
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#endif
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struct pci_dev_reset_methods {
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u16 vendor;
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u16 device;
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int (*reset)(struct pci_dev *dev, int probe);
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};
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#ifdef CONFIG_PCI_QUIRKS
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int pci_dev_specific_reset(struct pci_dev *dev, int probe);
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#else
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static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
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{
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return -ENOTTY;
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}
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#endif
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#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
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int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
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struct resource *res);
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#endif
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#endif /* DRIVERS_PCI_H */
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