753 lines
18 KiB
C
753 lines
18 KiB
C
/*
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* Copyright 2009 Pengutronix
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* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
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*
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* loosely based on an earlier driver that has
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* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*/
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/mutex.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/mc13783.h>
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struct mc13783 {
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struct spi_device *spidev;
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struct mutex lock;
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int irq;
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int flags;
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irq_handler_t irqhandler[MC13783_NUM_IRQ];
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void *irqdata[MC13783_NUM_IRQ];
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/* XXX these should go as platformdata to the regulator subdevice */
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struct mc13783_regulator_init_data *regulators;
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int num_regulators;
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};
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#define MC13783_REG_REVISION 7
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#define MC13783_REG_ADC_0 43
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#define MC13783_REG_ADC_1 44
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#define MC13783_REG_ADC_2 45
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#define MC13783_IRQSTAT0 0
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#define MC13783_IRQSTAT0_ADCDONEI (1 << 0)
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#define MC13783_IRQSTAT0_ADCBISDONEI (1 << 1)
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#define MC13783_IRQSTAT0_TSI (1 << 2)
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#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
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#define MC13783_IRQSTAT0_WLOWI (1 << 4)
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#define MC13783_IRQSTAT0_CHGDETI (1 << 6)
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#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
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#define MC13783_IRQSTAT0_CHGREVI (1 << 8)
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#define MC13783_IRQSTAT0_CHGSHORTI (1 << 9)
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#define MC13783_IRQSTAT0_CCCVI (1 << 10)
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#define MC13783_IRQSTAT0_CHGCURRI (1 << 11)
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#define MC13783_IRQSTAT0_BPONI (1 << 12)
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#define MC13783_IRQSTAT0_LOBATLI (1 << 13)
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#define MC13783_IRQSTAT0_LOBATHI (1 << 14)
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#define MC13783_IRQSTAT0_UDPI (1 << 15)
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#define MC13783_IRQSTAT0_USBI (1 << 16)
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#define MC13783_IRQSTAT0_IDI (1 << 19)
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#define MC13783_IRQSTAT0_SE1I (1 << 21)
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#define MC13783_IRQSTAT0_CKDETI (1 << 22)
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#define MC13783_IRQSTAT0_UDMI (1 << 23)
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#define MC13783_IRQMASK0 1
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#define MC13783_IRQMASK0_ADCDONEM MC13783_IRQSTAT0_ADCDONEI
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#define MC13783_IRQMASK0_ADCBISDONEM MC13783_IRQSTAT0_ADCBISDONEI
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#define MC13783_IRQMASK0_TSM MC13783_IRQSTAT0_TSI
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#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
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#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
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#define MC13783_IRQMASK0_CHGDETM MC13783_IRQSTAT0_CHGDETI
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#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
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#define MC13783_IRQMASK0_CHGREVM MC13783_IRQSTAT0_CHGREVI
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#define MC13783_IRQMASK0_CHGSHORTM MC13783_IRQSTAT0_CHGSHORTI
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#define MC13783_IRQMASK0_CCCVM MC13783_IRQSTAT0_CCCVI
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#define MC13783_IRQMASK0_CHGCURRM MC13783_IRQSTAT0_CHGCURRI
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#define MC13783_IRQMASK0_BPONM MC13783_IRQSTAT0_BPONI
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#define MC13783_IRQMASK0_LOBATLM MC13783_IRQSTAT0_LOBATLI
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#define MC13783_IRQMASK0_LOBATHM MC13783_IRQSTAT0_LOBATHI
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#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
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#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
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#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
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#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
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#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
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#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
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#define MC13783_IRQSTAT1 3
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#define MC13783_IRQSTAT1_1HZI (1 << 0)
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#define MC13783_IRQSTAT1_TODAI (1 << 1)
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#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
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#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
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#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
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#define MC13783_IRQSTAT1_SYSRSTI (1 << 6)
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#define MC13783_IRQSTAT1_RTCRSTI (1 << 7)
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#define MC13783_IRQSTAT1_PCI (1 << 8)
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#define MC13783_IRQSTAT1_WARMI (1 << 9)
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#define MC13783_IRQSTAT1_MEMHLDI (1 << 10)
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#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
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#define MC13783_IRQSTAT1_THWARNLI (1 << 12)
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#define MC13783_IRQSTAT1_THWARNHI (1 << 13)
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#define MC13783_IRQSTAT1_CLKI (1 << 14)
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#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
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#define MC13783_IRQSTAT1_MC2BI (1 << 17)
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#define MC13783_IRQSTAT1_HSDETI (1 << 18)
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#define MC13783_IRQSTAT1_HSLI (1 << 19)
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#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
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#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
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#define MC13783_IRQMASK1 4
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#define MC13783_IRQMASK1_1HZM MC13783_IRQSTAT1_1HZI
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#define MC13783_IRQMASK1_TODAM MC13783_IRQSTAT1_TODAI
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#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
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#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
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#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
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#define MC13783_IRQMASK1_SYSRSTM MC13783_IRQSTAT1_SYSRSTI
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#define MC13783_IRQMASK1_RTCRSTM MC13783_IRQSTAT1_RTCRSTI
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#define MC13783_IRQMASK1_PCM MC13783_IRQSTAT1_PCI
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#define MC13783_IRQMASK1_WARMM MC13783_IRQSTAT1_WARMI
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#define MC13783_IRQMASK1_MEMHLDM MC13783_IRQSTAT1_MEMHLDI
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#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
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#define MC13783_IRQMASK1_THWARNLM MC13783_IRQSTAT1_THWARNLI
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#define MC13783_IRQMASK1_THWARNHM MC13783_IRQSTAT1_THWARNHI
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#define MC13783_IRQMASK1_CLKM MC13783_IRQSTAT1_CLKI
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#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
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#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
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#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
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#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
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#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
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#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
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#define MC13783_ADC1 44
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#define MC13783_ADC1_ADEN (1 << 0)
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#define MC13783_ADC1_RAND (1 << 1)
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#define MC13783_ADC1_ADSEL (1 << 3)
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#define MC13783_ADC1_ASC (1 << 20)
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#define MC13783_ADC1_ADTRIGIGN (1 << 21)
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#define MC13783_NUMREGS 0x3f
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void mc13783_lock(struct mc13783 *mc13783)
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{
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if (!mutex_trylock(&mc13783->lock)) {
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dev_dbg(&mc13783->spidev->dev, "wait for %s from %pf\n",
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__func__, __builtin_return_address(0));
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mutex_lock(&mc13783->lock);
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}
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dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
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__func__, __builtin_return_address(0));
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}
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EXPORT_SYMBOL(mc13783_lock);
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void mc13783_unlock(struct mc13783 *mc13783)
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{
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dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
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__func__, __builtin_return_address(0));
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mutex_unlock(&mc13783->lock);
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}
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EXPORT_SYMBOL(mc13783_unlock);
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#define MC13783_REGOFFSET_SHIFT 25
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int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val)
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{
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struct spi_transfer t;
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struct spi_message m;
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int ret;
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BUG_ON(!mutex_is_locked(&mc13783->lock));
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if (offset > MC13783_NUMREGS)
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return -EINVAL;
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*val = offset << MC13783_REGOFFSET_SHIFT;
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memset(&t, 0, sizeof(t));
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t.tx_buf = val;
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t.rx_buf = val;
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t.len = sizeof(u32);
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spi_message_init(&m);
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spi_message_add_tail(&t, &m);
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ret = spi_sync(mc13783->spidev, &m);
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/* error in message.status implies error return from spi_sync */
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BUG_ON(!ret && m.status);
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if (ret)
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return ret;
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*val &= 0xffffff;
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dev_vdbg(&mc13783->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
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return 0;
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}
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EXPORT_SYMBOL(mc13783_reg_read);
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int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val)
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{
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u32 buf;
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struct spi_transfer t;
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struct spi_message m;
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int ret;
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BUG_ON(!mutex_is_locked(&mc13783->lock));
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dev_vdbg(&mc13783->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
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if (offset > MC13783_NUMREGS || val > 0xffffff)
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return -EINVAL;
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buf = 1 << 31 | offset << MC13783_REGOFFSET_SHIFT | val;
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memset(&t, 0, sizeof(t));
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t.tx_buf = &buf;
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t.rx_buf = &buf;
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t.len = sizeof(u32);
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spi_message_init(&m);
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spi_message_add_tail(&t, &m);
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ret = spi_sync(mc13783->spidev, &m);
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BUG_ON(!ret && m.status);
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if (ret)
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return ret;
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return 0;
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}
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EXPORT_SYMBOL(mc13783_reg_write);
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int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
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u32 mask, u32 val)
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{
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int ret;
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u32 valread;
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BUG_ON(val & ~mask);
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ret = mc13783_reg_read(mc13783, offset, &valread);
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if (ret)
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return ret;
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valread = (valread & ~mask) | val;
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return mc13783_reg_write(mc13783, offset, valread);
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}
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EXPORT_SYMBOL(mc13783_reg_rmw);
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int mc13783_get_flags(struct mc13783 *mc13783)
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{
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return mc13783->flags;
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}
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EXPORT_SYMBOL(mc13783_get_flags);
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int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
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{
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int ret;
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unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
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u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
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u32 mask;
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if (irq < 0 || irq >= MC13783_NUM_IRQ)
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return -EINVAL;
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ret = mc13783_reg_read(mc13783, offmask, &mask);
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if (ret)
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return ret;
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if (mask & irqbit)
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/* already masked */
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return 0;
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return mc13783_reg_write(mc13783, offmask, mask | irqbit);
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}
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EXPORT_SYMBOL(mc13783_irq_mask);
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int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
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{
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int ret;
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unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
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u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
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u32 mask;
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if (irq < 0 || irq >= MC13783_NUM_IRQ)
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return -EINVAL;
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ret = mc13783_reg_read(mc13783, offmask, &mask);
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if (ret)
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return ret;
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if (!(mask & irqbit))
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/* already unmasked */
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return 0;
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return mc13783_reg_write(mc13783, offmask, mask & ~irqbit);
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}
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EXPORT_SYMBOL(mc13783_irq_unmask);
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int mc13783_irq_status(struct mc13783 *mc13783, int irq,
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int *enabled, int *pending)
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{
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int ret;
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unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
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unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
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u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
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if (irq < 0 || irq >= MC13783_NUM_IRQ)
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return -EINVAL;
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if (enabled) {
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u32 mask;
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ret = mc13783_reg_read(mc13783, offmask, &mask);
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if (ret)
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return ret;
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*enabled = mask & irqbit;
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}
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if (pending) {
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u32 stat;
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ret = mc13783_reg_read(mc13783, offstat, &stat);
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if (ret)
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return ret;
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*pending = stat & irqbit;
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}
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return 0;
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}
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EXPORT_SYMBOL(mc13783_irq_status);
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int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
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{
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unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
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unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
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BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ);
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return mc13783_reg_write(mc13783, offstat, val);
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}
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EXPORT_SYMBOL(mc13783_irq_ack);
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int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
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irq_handler_t handler, const char *name, void *dev)
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{
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BUG_ON(!mutex_is_locked(&mc13783->lock));
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BUG_ON(!handler);
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if (irq < 0 || irq >= MC13783_NUM_IRQ)
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return -EINVAL;
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if (mc13783->irqhandler[irq])
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return -EBUSY;
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mc13783->irqhandler[irq] = handler;
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mc13783->irqdata[irq] = dev;
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return 0;
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}
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EXPORT_SYMBOL(mc13783_irq_request_nounmask);
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int mc13783_irq_request(struct mc13783 *mc13783, int irq,
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irq_handler_t handler, const char *name, void *dev)
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{
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int ret;
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ret = mc13783_irq_request_nounmask(mc13783, irq, handler, name, dev);
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if (ret)
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return ret;
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ret = mc13783_irq_unmask(mc13783, irq);
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if (ret) {
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mc13783->irqhandler[irq] = NULL;
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mc13783->irqdata[irq] = NULL;
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL(mc13783_irq_request);
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int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
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{
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int ret;
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BUG_ON(!mutex_is_locked(&mc13783->lock));
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if (irq < 0 || irq >= MC13783_NUM_IRQ || !mc13783->irqhandler[irq] ||
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mc13783->irqdata[irq] != dev)
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return -EINVAL;
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ret = mc13783_irq_mask(mc13783, irq);
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if (ret)
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return ret;
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mc13783->irqhandler[irq] = NULL;
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mc13783->irqdata[irq] = NULL;
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return 0;
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}
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EXPORT_SYMBOL(mc13783_irq_free);
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static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq)
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{
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return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]);
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}
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/*
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* returns: number of handled irqs or negative error
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* locking: holds mc13783->lock
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*/
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static int mc13783_irq_handle(struct mc13783 *mc13783,
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unsigned int offstat, unsigned int offmask, int baseirq)
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{
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u32 stat, mask;
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int ret = mc13783_reg_read(mc13783, offstat, &stat);
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int num_handled = 0;
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if (ret)
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return ret;
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ret = mc13783_reg_read(mc13783, offmask, &mask);
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if (ret)
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return ret;
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while (stat & ~mask) {
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int irq = __ffs(stat & ~mask);
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stat &= ~(1 << irq);
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if (likely(mc13783->irqhandler[baseirq + irq])) {
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irqreturn_t handled;
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handled = mc13783_irqhandler(mc13783, baseirq + irq);
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if (handled == IRQ_HANDLED)
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num_handled++;
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} else {
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dev_err(&mc13783->spidev->dev,
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"BUG: irq %u but no handler\n",
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baseirq + irq);
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mask |= 1 << irq;
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ret = mc13783_reg_write(mc13783, offmask, mask);
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}
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}
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return num_handled;
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}
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static irqreturn_t mc13783_irq_thread(int irq, void *data)
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{
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struct mc13783 *mc13783 = data;
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irqreturn_t ret;
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int handled = 0;
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mc13783_lock(mc13783);
|
|
|
|
ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT0,
|
|
MC13783_IRQMASK0, MC13783_IRQ_ADCDONE);
|
|
if (ret > 0)
|
|
handled = 1;
|
|
|
|
ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT1,
|
|
MC13783_IRQMASK1, MC13783_IRQ_1HZ);
|
|
if (ret > 0)
|
|
handled = 1;
|
|
|
|
mc13783_unlock(mc13783);
|
|
|
|
return IRQ_RETVAL(handled);
|
|
}
|
|
|
|
#define MC13783_ADC1_CHAN0_SHIFT 5
|
|
#define MC13783_ADC1_CHAN1_SHIFT 8
|
|
|
|
struct mc13783_adcdone_data {
|
|
struct mc13783 *mc13783;
|
|
struct completion done;
|
|
};
|
|
|
|
static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
|
|
{
|
|
struct mc13783_adcdone_data *adcdone_data = data;
|
|
|
|
mc13783_irq_ack(adcdone_data->mc13783, irq);
|
|
|
|
complete_all(&adcdone_data->done);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#define MC13783_ADC_WORKING (1 << 16)
|
|
|
|
int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
|
|
unsigned int channel, unsigned int *sample)
|
|
{
|
|
u32 adc0, adc1, old_adc0;
|
|
int i, ret;
|
|
struct mc13783_adcdone_data adcdone_data = {
|
|
.mc13783 = mc13783,
|
|
};
|
|
init_completion(&adcdone_data.done);
|
|
|
|
dev_dbg(&mc13783->spidev->dev, "%s\n", __func__);
|
|
|
|
mc13783_lock(mc13783);
|
|
|
|
if (mc13783->flags & MC13783_ADC_WORKING) {
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
|
|
mc13783->flags |= MC13783_ADC_WORKING;
|
|
|
|
mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0);
|
|
|
|
adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
|
|
adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
|
|
|
|
if (channel > 7)
|
|
adc1 |= MC13783_ADC1_ADSEL;
|
|
|
|
switch (mode) {
|
|
case MC13783_ADC_MODE_TS:
|
|
adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
|
|
MC13783_ADC0_TSMOD1;
|
|
adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
|
|
break;
|
|
|
|
case MC13783_ADC_MODE_SINGLE_CHAN:
|
|
adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
|
|
adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
|
|
adc1 |= MC13783_ADC1_RAND;
|
|
break;
|
|
|
|
case MC13783_ADC_MODE_MULT_CHAN:
|
|
adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
|
|
adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
|
|
break;
|
|
|
|
default:
|
|
mc13783_unlock(mc13783);
|
|
return -EINVAL;
|
|
}
|
|
|
|
dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__);
|
|
mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE,
|
|
mc13783_handler_adcdone, __func__, &adcdone_data);
|
|
mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE);
|
|
|
|
mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0);
|
|
mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1);
|
|
|
|
mc13783_unlock(mc13783);
|
|
|
|
ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
|
|
|
|
if (!ret)
|
|
ret = -ETIMEDOUT;
|
|
|
|
mc13783_lock(mc13783);
|
|
|
|
mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data);
|
|
|
|
if (ret > 0)
|
|
for (i = 0; i < 4; ++i) {
|
|
ret = mc13783_reg_read(mc13783,
|
|
MC13783_REG_ADC_2, &sample[i]);
|
|
if (ret)
|
|
break;
|
|
}
|
|
|
|
if (mode == MC13783_ADC_MODE_TS)
|
|
/* restore TSMOD */
|
|
mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0);
|
|
|
|
mc13783->flags &= ~MC13783_ADC_WORKING;
|
|
out:
|
|
mc13783_unlock(mc13783);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
|
|
|
|
static int mc13783_add_subdevice_pdata(struct mc13783 *mc13783,
|
|
const char *name, void *pdata, size_t pdata_size)
|
|
{
|
|
struct mfd_cell cell = {
|
|
.name = name,
|
|
.platform_data = pdata,
|
|
.data_size = pdata_size,
|
|
};
|
|
|
|
return mfd_add_devices(&mc13783->spidev->dev, -1, &cell, 1, NULL, 0);
|
|
}
|
|
|
|
static int mc13783_add_subdevice(struct mc13783 *mc13783, const char *name)
|
|
{
|
|
return mc13783_add_subdevice_pdata(mc13783, name, NULL, 0);
|
|
}
|
|
|
|
static int mc13783_check_revision(struct mc13783 *mc13783)
|
|
{
|
|
u32 rev_id, rev1, rev2, finid, icid;
|
|
|
|
mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id);
|
|
|
|
rev1 = (rev_id & 0x018) >> 3;
|
|
rev2 = (rev_id & 0x007);
|
|
icid = (rev_id & 0x01C0) >> 6;
|
|
finid = (rev_id & 0x01E00) >> 9;
|
|
|
|
/* Ver 0.2 is actually 3.2a. Report as 3.2 */
|
|
if ((rev1 == 0) && (rev2 == 2))
|
|
rev1 = 3;
|
|
|
|
if (rev1 == 0 || icid != 2) {
|
|
dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
dev_info(&mc13783->spidev->dev,
|
|
"MC13783 Rev %d.%d FinVer %x detected\n",
|
|
rev1, rev2, finid);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mc13783_probe(struct spi_device *spi)
|
|
{
|
|
struct mc13783 *mc13783;
|
|
struct mc13783_platform_data *pdata = dev_get_platdata(&spi->dev);
|
|
int ret;
|
|
|
|
mc13783 = kzalloc(sizeof(*mc13783), GFP_KERNEL);
|
|
if (!mc13783)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(&spi->dev, mc13783);
|
|
spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
|
|
spi->bits_per_word = 32;
|
|
spi_setup(spi);
|
|
|
|
mc13783->spidev = spi;
|
|
|
|
mutex_init(&mc13783->lock);
|
|
mc13783_lock(mc13783);
|
|
|
|
ret = mc13783_check_revision(mc13783);
|
|
if (ret)
|
|
goto err_revision;
|
|
|
|
/* mask all irqs */
|
|
ret = mc13783_reg_write(mc13783, MC13783_IRQMASK0, 0x00ffffff);
|
|
if (ret)
|
|
goto err_mask;
|
|
|
|
ret = mc13783_reg_write(mc13783, MC13783_IRQMASK1, 0x00ffffff);
|
|
if (ret)
|
|
goto err_mask;
|
|
|
|
ret = request_threaded_irq(spi->irq, NULL, mc13783_irq_thread,
|
|
IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13783", mc13783);
|
|
|
|
if (ret) {
|
|
err_mask:
|
|
err_revision:
|
|
mutex_unlock(&mc13783->lock);
|
|
dev_set_drvdata(&spi->dev, NULL);
|
|
kfree(mc13783);
|
|
return ret;
|
|
}
|
|
|
|
/* This should go away (BEGIN) */
|
|
if (pdata) {
|
|
mc13783->flags = pdata->flags;
|
|
mc13783->regulators = pdata->regulators;
|
|
mc13783->num_regulators = pdata->num_regulators;
|
|
}
|
|
/* This should go away (END) */
|
|
|
|
mc13783_unlock(mc13783);
|
|
|
|
if (pdata->flags & MC13783_USE_ADC)
|
|
mc13783_add_subdevice(mc13783, "mc13783-adc");
|
|
|
|
if (pdata->flags & MC13783_USE_CODEC)
|
|
mc13783_add_subdevice(mc13783, "mc13783-codec");
|
|
|
|
if (pdata->flags & MC13783_USE_REGULATOR) {
|
|
struct mc13783_regulator_platform_data regulator_pdata = {
|
|
.num_regulators = pdata->num_regulators,
|
|
.regulators = pdata->regulators,
|
|
};
|
|
|
|
mc13783_add_subdevice_pdata(mc13783, "mc13783-regulator",
|
|
®ulator_pdata, sizeof(regulator_pdata));
|
|
}
|
|
|
|
if (pdata->flags & MC13783_USE_RTC)
|
|
mc13783_add_subdevice(mc13783, "mc13783-rtc");
|
|
|
|
if (pdata->flags & MC13783_USE_TOUCHSCREEN)
|
|
mc13783_add_subdevice(mc13783, "mc13783-ts");
|
|
|
|
if (pdata->flags & MC13783_USE_LED)
|
|
mc13783_add_subdevice_pdata(mc13783, "mc13783-led",
|
|
pdata->leds, sizeof(*pdata->leds));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __devexit mc13783_remove(struct spi_device *spi)
|
|
{
|
|
struct mc13783 *mc13783 = dev_get_drvdata(&spi->dev);
|
|
|
|
free_irq(mc13783->spidev->irq, mc13783);
|
|
|
|
mfd_remove_devices(&spi->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct spi_driver mc13783_driver = {
|
|
.driver = {
|
|
.name = "mc13783",
|
|
.bus = &spi_bus_type,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = mc13783_probe,
|
|
.remove = __devexit_p(mc13783_remove),
|
|
};
|
|
|
|
static int __init mc13783_init(void)
|
|
{
|
|
return spi_register_driver(&mc13783_driver);
|
|
}
|
|
subsys_initcall(mc13783_init);
|
|
|
|
static void __exit mc13783_exit(void)
|
|
{
|
|
spi_unregister_driver(&mc13783_driver);
|
|
}
|
|
module_exit(mc13783_exit);
|
|
|
|
MODULE_DESCRIPTION("Core driver for Freescale MC13783 PMIC");
|
|
MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
|
|
MODULE_LICENSE("GPL v2");
|