633 lines
13 KiB
C
633 lines
13 KiB
C
/*
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* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/math64.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/clock.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include "crm_regs.h"
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static int _clk_enable(struct clk *clk)
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{
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unsigned int reg;
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reg = __raw_readl(clk->enable_reg);
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reg |= 1 << clk->enable_shift;
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__raw_writel(reg, clk->enable_reg);
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return 0;
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}
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static void _clk_disable(struct clk *clk)
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{
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unsigned int reg;
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reg = __raw_readl(clk->enable_reg);
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reg &= ~(1 << clk->enable_shift);
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__raw_writel(reg, clk->enable_reg);
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}
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static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
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struct clk *parent)
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{
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int i;
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for (i = 0; i < size; i++)
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if (parent == clk_arr[i])
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return i;
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return -EINVAL;
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}
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static unsigned long
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_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
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{
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int div;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (parent_rate % rate)
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div++;
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if (div > limit)
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div = limit;
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return parent_rate / div;
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}
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static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk->parent->round_rate(clk->parent, rate);
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}
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static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
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{
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return clk->parent->set_rate(clk->parent, rate);
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}
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static unsigned long clk16m_get_rate(struct clk *clk)
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{
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return 16000000;
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}
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static struct clk clk16m = {
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.name = "CLK16M",
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.get_rate = clk16m_get_rate,
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.enable = _clk_enable,
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.enable_reg = CCM_CSCR,
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.enable_shift = CCM_CSCR_OSC_EN_SHIFT,
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.disable = _clk_disable,
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};
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/* in Hz */
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static unsigned long clk32_rate;
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static unsigned long clk32_get_rate(struct clk *clk)
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{
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return clk32_rate;
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}
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static struct clk clk32 = {
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.name = "CLK32",
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.get_rate = clk32_get_rate,
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};
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static unsigned long clk32_premult_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) * 512;
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}
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static struct clk clk32_premult = {
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.name = "CLK32_premultiplier",
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.parent = &clk32,
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.get_rate = clk32_premult_get_rate,
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};
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static const struct clk *prem_clk_clocks[] = {
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&clk32_premult,
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&clk16m,
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};
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static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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int i;
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unsigned int reg = __raw_readl(CCM_CSCR);
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i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
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parent);
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switch (i) {
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case 0:
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reg &= ~CCM_CSCR_SYSTEM_SEL;
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break;
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case 1:
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reg |= CCM_CSCR_SYSTEM_SEL;
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break;
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default:
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return i;
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}
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__raw_writel(reg, CCM_CSCR);
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return 0;
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}
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static struct clk prem_clk = {
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.name = "prem_clk",
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.set_parent = prem_clk_set_parent,
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};
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static unsigned long system_clk_get_rate(struct clk *clk)
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{
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return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
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clk_get_rate(clk->parent));
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}
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static struct clk system_clk = {
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.name = "system_clk",
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.parent = &prem_clk,
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.get_rate = system_clk_get_rate,
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};
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static unsigned long mcu_clk_get_rate(struct clk *clk)
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{
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return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
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clk_get_rate(clk->parent));
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}
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static struct clk mcu_clk = {
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.name = "mcu_clk",
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.parent = &clk32_premult,
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.get_rate = mcu_clk_get_rate,
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};
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static unsigned long fclk_get_rate(struct clk *clk)
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{
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unsigned long fclk = clk_get_rate(clk->parent);
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if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
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fclk /= 2;
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return fclk;
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}
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static struct clk fclk = {
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.name = "fclk",
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.parent = &mcu_clk,
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.get_rate = fclk_get_rate,
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};
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/*
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* get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
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*/
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static unsigned long hclk_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
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CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
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}
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static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 16);
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}
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static int hclk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 16 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_CSCR);
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reg &= ~CCM_CSCR_BCLK_MASK;
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reg |= div << CCM_CSCR_BCLK_OFFSET;
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__raw_writel(reg, CCM_CSCR);
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return 0;
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}
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static struct clk hclk = {
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.name = "hclk",
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.parent = &system_clk,
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.get_rate = hclk_get_rate,
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.round_rate = hclk_round_rate,
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.set_rate = hclk_set_rate,
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};
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static unsigned long clk48m_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
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CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
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}
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static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 8);
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}
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static int clk48m_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 8 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_CSCR);
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reg &= ~CCM_CSCR_USB_MASK;
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reg |= div << CCM_CSCR_USB_OFFSET;
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__raw_writel(reg, CCM_CSCR);
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return 0;
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}
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static struct clk clk48m = {
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.name = "CLK48M",
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.parent = &system_clk,
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.get_rate = clk48m_get_rate,
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.round_rate = clk48m_round_rate,
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.set_rate = clk48m_set_rate,
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};
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/*
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* get peripheral clock 1 ( UART[12], Timer[12], PWM )
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*/
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static unsigned long perclk1_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
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CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
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}
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static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 16);
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}
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static int perclk1_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 16 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_PCDR);
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reg &= ~CCM_PCDR_PCLK1_MASK;
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reg |= div << CCM_PCDR_PCLK1_OFFSET;
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__raw_writel(reg, CCM_PCDR);
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return 0;
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}
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/*
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* get peripheral clock 2 ( LCD, SD, SPI[12] )
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*/
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static unsigned long perclk2_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
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CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
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}
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static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 16);
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}
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static int perclk2_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 16 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_PCDR);
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reg &= ~CCM_PCDR_PCLK2_MASK;
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reg |= div << CCM_PCDR_PCLK2_OFFSET;
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__raw_writel(reg, CCM_PCDR);
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return 0;
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}
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/*
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* get peripheral clock 3 ( SSI )
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*/
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static unsigned long perclk3_get_rate(struct clk *clk)
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{
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return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
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CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
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}
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static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
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{
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return _clk_simple_round_rate(clk, rate, 128);
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}
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static int perclk3_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned int div;
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unsigned int reg;
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unsigned long parent_rate;
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parent_rate = clk_get_rate(clk->parent);
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div = parent_rate / rate;
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if (div > 128 || div < 1 || ((parent_rate / div) != rate))
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return -EINVAL;
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div--;
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reg = __raw_readl(CCM_PCDR);
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reg &= ~CCM_PCDR_PCLK3_MASK;
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reg |= div << CCM_PCDR_PCLK3_OFFSET;
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__raw_writel(reg, CCM_PCDR);
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return 0;
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}
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static struct clk perclk[] = {
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{
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.name = "perclk",
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.id = 0,
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.parent = &system_clk,
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.get_rate = perclk1_get_rate,
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.round_rate = perclk1_round_rate,
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.set_rate = perclk1_set_rate,
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}, {
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.name = "perclk",
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.id = 1,
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.parent = &system_clk,
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.get_rate = perclk2_get_rate,
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.round_rate = perclk2_round_rate,
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.set_rate = perclk2_set_rate,
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}, {
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.name = "perclk",
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.id = 2,
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.parent = &system_clk,
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.get_rate = perclk3_get_rate,
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.round_rate = perclk3_round_rate,
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.set_rate = perclk3_set_rate,
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}
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};
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static const struct clk *clko_clocks[] = {
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&perclk[0],
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&hclk,
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&clk48m,
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&clk16m,
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&prem_clk,
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&fclk,
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};
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static int clko_set_parent(struct clk *clk, struct clk *parent)
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{
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int i;
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unsigned int reg;
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i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
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if (i < 0)
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return i;
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reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
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reg |= i << CCM_CSCR_CLKO_OFFSET;
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__raw_writel(reg, CCM_CSCR);
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if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
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clk->set_rate = _clk_parent_set_rate;
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clk->round_rate = _clk_parent_round_rate;
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} else {
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clk->set_rate = NULL;
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clk->round_rate = NULL;
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}
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return 0;
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}
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static struct clk clko_clk = {
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.name = "clko_clk",
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.set_parent = clko_set_parent,
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};
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static struct clk dma_clk = {
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.name = "dma",
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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.enable = _clk_enable,
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.enable_reg = SCM_GCCR,
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.enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
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.disable = _clk_disable,
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};
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static struct clk csi_clk = {
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.name = "csi_clk",
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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.enable = _clk_enable,
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.enable_reg = SCM_GCCR,
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.enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
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.disable = _clk_disable,
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};
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static struct clk mma_clk = {
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.name = "mma_clk",
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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.enable = _clk_enable,
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.enable_reg = SCM_GCCR,
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.enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
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.disable = _clk_disable,
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};
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static struct clk usbd_clk = {
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.name = "usbd_clk",
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.parent = &clk48m,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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.enable = _clk_enable,
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.enable_reg = SCM_GCCR,
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.enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
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.disable = _clk_disable,
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};
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static struct clk gpt_clk = {
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.name = "gpt_clk",
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.parent = &perclk[0],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk uart_clk = {
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.name = "uart",
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.parent = &perclk[0],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk i2c_clk = {
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.name = "i2c_clk",
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.parent = &hclk,
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk spi_clk = {
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.name = "spi_clk",
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.parent = &perclk[1],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk sdhc_clk = {
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.name = "sdhc_clk",
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.parent = &perclk[1],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.parent = &perclk[1],
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.round_rate = _clk_parent_round_rate,
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.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk mshc_clk = {
|
|
.name = "mshc_clk",
|
|
.parent = &hclk,
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk ssi_clk = {
|
|
.name = "ssi_clk",
|
|
.parent = &perclk[2],
|
|
.round_rate = _clk_parent_round_rate,
|
|
.set_rate = _clk_parent_set_rate,
|
|
};
|
|
|
|
static struct clk rtc_clk = {
|
|
.name = "rtc_clk",
|
|
.parent = &clk32,
|
|
};
|
|
|
|
static struct clk *mxc_clks[] = {
|
|
&clk16m,
|
|
&clk32,
|
|
&clk32_premult,
|
|
&prem_clk,
|
|
&system_clk,
|
|
&mcu_clk,
|
|
&fclk,
|
|
&hclk,
|
|
&clk48m,
|
|
&perclk[0],
|
|
&perclk[1],
|
|
&perclk[2],
|
|
&clko_clk,
|
|
&dma_clk,
|
|
&csi_clk,
|
|
&mma_clk,
|
|
&usbd_clk,
|
|
&gpt_clk,
|
|
&uart_clk,
|
|
&i2c_clk,
|
|
&spi_clk,
|
|
&sdhc_clk,
|
|
&lcdc_clk,
|
|
&mshc_clk,
|
|
&ssi_clk,
|
|
&rtc_clk,
|
|
};
|
|
|
|
int __init mx1_clocks_init(unsigned long fref)
|
|
{
|
|
struct clk **clkp;
|
|
unsigned int reg;
|
|
|
|
/* disable clocks we are able to */
|
|
__raw_writel(0, SCM_GCCR);
|
|
|
|
clk32_rate = fref;
|
|
reg = __raw_readl(CCM_CSCR);
|
|
|
|
/* detect clock reference for system PLL */
|
|
if (reg & CCM_CSCR_SYSTEM_SEL) {
|
|
prem_clk.parent = &clk16m;
|
|
} else {
|
|
/* ensure that oscillator is disabled */
|
|
reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
|
|
__raw_writel(reg, CCM_CSCR);
|
|
prem_clk.parent = &clk32_premult;
|
|
}
|
|
|
|
/* detect reference for CLKO */
|
|
reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
|
|
clko_clk.parent = (struct clk *)clko_clocks[reg];
|
|
|
|
for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
|
|
clk_register(*clkp);
|
|
|
|
clk_enable(&hclk);
|
|
clk_enable(&fclk);
|
|
|
|
mxc_timer_init(&gpt_clk);
|
|
|
|
return 0;
|
|
}
|