209 lines
5.2 KiB
ArmAsm
209 lines
5.2 KiB
ArmAsm
#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/cache.h>
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#include <mach/iomap.h>
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#include "flowctrl.h"
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#include "reset.h"
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#include "sleep.h"
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#define APB_MISC_GP_HIDREV 0x804
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#define PMC_SCRATCH41 0x140
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#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
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.section ".text.head", "ax"
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__CPUINIT
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/*
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* Tegra specific entry point for secondary CPUs.
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* The secondary kernel init calls v7_flush_dcache_all before it enables
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* the L1; however, the L1 comes out of reset in an undefined state, so
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* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
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* of cache lines with uninitialized data and uninitialized tags to get
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* written out to memory, which does really unpleasant things to the main
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* processor. We fix this by performing an invalidate, rather than a
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* clean + invalidate, before jumping into the kernel.
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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ENTRY(tegra_secondary_startup)
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bl v7_invalidate_l1
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/* Enable coresight */
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mov32 r0, 0xC5ACCE55
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mcr p14, 0, r0, c7, c12, 6
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b secondary_startup
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ENDPROC(tegra_secondary_startup)
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.align L1_CACHE_SHIFT
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ENTRY(__tegra_cpu_reset_handler_start)
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/*
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* __tegra_cpu_reset_handler:
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*
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* Common handler for all CPU reset events.
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*
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* Register usage within the reset handler:
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*
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* R7 = CPU present (to the OS) mask
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* R8 = CPU in LP1 state mask
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* R9 = CPU in LP2 state mask
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* R10 = CPU number
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* R11 = CPU mask
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* R12 = pointer to reset handler data
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*
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* NOTE: This code is copied to IRAM. All code and data accesses
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* must be position-independent.
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*/
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.align L1_CACHE_SHIFT
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ENTRY(__tegra_cpu_reset_handler)
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cpsid aif, 0x13 @ SVC mode, interrupts disabled
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mrc p15, 0, r10, c0, c0, 5 @ MPIDR
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and r10, r10, #0x3 @ R10 = CPU number
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mov r11, #1
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mov r11, r11, lsl r10 @ R11 = CPU mask
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adr r12, __tegra_cpu_reset_handler_data
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#ifdef CONFIG_SMP
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/* Does the OS know about this CPU? */
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ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
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tst r7, r11 @ if !present
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bleq __die @ CPU not present (to OS)
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#endif
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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/* Are we on Tegra20? */
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mov32 r6, TEGRA_APB_MISC_BASE
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ldr r0, [r6, #APB_MISC_GP_HIDREV]
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and r0, r0, #0xff00
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cmp r0, #(0x20 << 8)
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bne 1f
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/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
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mov32 r6, TEGRA_PMC_BASE
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mov r0, #0
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cmp r10, #0
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strne r0, [r6, #PMC_SCRATCH41]
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1:
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#endif
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#ifdef CONFIG_SMP
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/*
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* Can only be secondary boot (initial or hotplug) but CPU 0
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* cannot be here.
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*/
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cmp r10, #0
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bleq __die @ CPU0 cannot be here
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ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
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cmp lr, #0
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bleq __die @ no secondary startup handler
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bx lr
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#endif
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/*
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* We don't know why the CPU reset. Just kill it.
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* The LR register will contain the address we died at + 4.
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*/
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__die:
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sub lr, lr, #4
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mov32 r7, TEGRA_PMC_BASE
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str lr, [r7, #PMC_SCRATCH41]
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mov32 r7, TEGRA_CLK_RESET_BASE
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/* Are we on Tegra20? */
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mov32 r6, TEGRA_APB_MISC_BASE
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ldr r0, [r6, #APB_MISC_GP_HIDREV]
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and r0, r0, #0xff00
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cmp r0, #(0x20 << 8)
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bne 1f
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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mov32 r0, 0x1111
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mov r1, r0, lsl r10
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str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
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#endif
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1:
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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mov32 r6, TEGRA_FLOW_CTRL_BASE
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cmp r10, #0
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moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
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moveq r2, #FLOW_CTRL_CPU0_CSR
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movne r1, r10, lsl #3
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addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
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addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
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/* Clear CPU "event" and "interrupt" flags and power gate
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it when halting but not before it is in the "WFI" state. */
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ldr r0, [r6, +r2]
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orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
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orr r0, r0, #FLOW_CTRL_CSR_ENABLE
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str r0, [r6, +r2]
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/* Unconditionally halt this CPU */
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mov r0, #FLOW_CTRL_WAITEVENT
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str r0, [r6, +r1]
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ldr r0, [r6, +r1] @ memory barrier
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dsb
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isb
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wfi @ CPU should be power gated here
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/* If the CPU didn't power gate above just kill it's clock. */
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mov r0, r11, lsl #8
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str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
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#endif
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/* If the CPU still isn't dead, just spin here. */
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b .
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ENDPROC(__tegra_cpu_reset_handler)
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.align L1_CACHE_SHIFT
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.type __tegra_cpu_reset_handler_data, %object
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.globl __tegra_cpu_reset_handler_data
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__tegra_cpu_reset_handler_data:
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.rept TEGRA_RESET_DATA_SIZE
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.long 0
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.endr
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.align L1_CACHE_SHIFT
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ENTRY(__tegra_cpu_reset_handler_end)
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