1014 lines
25 KiB
C
1014 lines
25 KiB
C
/*
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* Copyright (C) 2005, 2006 IBM Corporation
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* Copyright (C) 2014 Intel Corporation
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*
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* Authors:
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* Leendert van Doorn <leendert@watson.ibm.com>
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* Kylene Hall <kjhall@us.ibm.com>
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*
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* Maintained by: <tpmdd-devel@lists.sourceforge.net>
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*
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* Device driver for TCG/TCPA TPM (trusted platform module).
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* Specifications at www.trustedcomputinggroup.org
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*
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* This device driver implements the TPM interface as defined in
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* the TCG TPM Interface Spec version 1.2, revision 1.0.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation, version 2 of the
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* License.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/pnp.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/wait.h>
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#include <linux/acpi.h>
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#include <linux/freezer.h>
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#include "tpm.h"
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enum tis_access {
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TPM_ACCESS_VALID = 0x80,
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TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
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TPM_ACCESS_REQUEST_PENDING = 0x04,
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TPM_ACCESS_REQUEST_USE = 0x02,
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};
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enum tis_status {
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TPM_STS_VALID = 0x80,
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TPM_STS_COMMAND_READY = 0x40,
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TPM_STS_GO = 0x20,
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TPM_STS_DATA_AVAIL = 0x10,
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TPM_STS_DATA_EXPECT = 0x08,
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};
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enum tis_int_flags {
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TPM_GLOBAL_INT_ENABLE = 0x80000000,
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TPM_INTF_BURST_COUNT_STATIC = 0x100,
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TPM_INTF_CMD_READY_INT = 0x080,
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TPM_INTF_INT_EDGE_FALLING = 0x040,
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TPM_INTF_INT_EDGE_RISING = 0x020,
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TPM_INTF_INT_LEVEL_LOW = 0x010,
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TPM_INTF_INT_LEVEL_HIGH = 0x008,
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TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
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TPM_INTF_STS_VALID_INT = 0x002,
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TPM_INTF_DATA_AVAIL_INT = 0x001,
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};
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enum tis_defaults {
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TIS_MEM_BASE = 0xFED40000,
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TIS_MEM_LEN = 0x5000,
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TIS_SHORT_TIMEOUT = 750, /* ms */
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TIS_LONG_TIMEOUT = 2000, /* 2 sec */
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};
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/* Some timeout values are needed before it is known whether the chip is
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* TPM 1.0 or TPM 2.0.
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*/
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#define TIS_TIMEOUT_A_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
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#define TIS_TIMEOUT_B_MAX max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
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#define TIS_TIMEOUT_C_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
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#define TIS_TIMEOUT_D_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
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#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
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#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
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#define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
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#define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
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#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
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#define TPM_STS(l) (0x0018 | ((l) << 12))
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#define TPM_STS3(l) (0x001b | ((l) << 12))
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#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
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#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
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#define TPM_RID(l) (0x0F04 | ((l) << 12))
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struct priv_data {
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bool irq_tested;
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};
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#if defined(CONFIG_PNP) && defined(CONFIG_ACPI)
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static int is_itpm(struct pnp_dev *dev)
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{
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struct acpi_device *acpi = pnp_acpi_device(dev);
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struct acpi_hardware_id *id;
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if (!acpi)
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return 0;
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list_for_each_entry(id, &acpi->pnp.ids, list) {
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if (!strcmp("INTC0102", id->id))
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return 1;
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}
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return 0;
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}
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#else
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static inline int is_itpm(struct pnp_dev *dev)
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{
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return 0;
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}
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#endif
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/* Before we attempt to access the TPM we must see that the valid bit is set.
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* The specification says that this bit is 0 at reset and remains 0 until the
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* 'TPM has gone through its self test and initialization and has established
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* correct values in the other bits.' */
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static int wait_startup(struct tpm_chip *chip, int l)
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{
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unsigned long stop = jiffies + chip->vendor.timeout_a;
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do {
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if (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
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TPM_ACCESS_VALID)
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return 0;
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msleep(TPM_TIMEOUT);
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} while (time_before(jiffies, stop));
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return -1;
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}
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static int check_locality(struct tpm_chip *chip, int l)
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{
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if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
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(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
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(TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
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return chip->vendor.locality = l;
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return -1;
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}
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static void release_locality(struct tpm_chip *chip, int l, int force)
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{
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if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
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(TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
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(TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
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iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
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chip->vendor.iobase + TPM_ACCESS(l));
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}
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static int request_locality(struct tpm_chip *chip, int l)
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{
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unsigned long stop, timeout;
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long rc;
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if (check_locality(chip, l) >= 0)
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return l;
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iowrite8(TPM_ACCESS_REQUEST_USE,
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chip->vendor.iobase + TPM_ACCESS(l));
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stop = jiffies + chip->vendor.timeout_a;
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if (chip->vendor.irq) {
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again:
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timeout = stop - jiffies;
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if ((long)timeout <= 0)
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return -1;
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rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
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(check_locality
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(chip, l) >= 0),
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timeout);
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if (rc > 0)
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return l;
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if (rc == -ERESTARTSYS && freezing(current)) {
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clear_thread_flag(TIF_SIGPENDING);
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goto again;
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}
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} else {
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/* wait for burstcount */
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do {
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if (check_locality(chip, l) >= 0)
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return l;
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msleep(TPM_TIMEOUT);
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}
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while (time_before(jiffies, stop));
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}
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return -1;
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}
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static u8 tpm_tis_status(struct tpm_chip *chip)
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{
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return ioread8(chip->vendor.iobase +
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TPM_STS(chip->vendor.locality));
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}
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static void tpm_tis_ready(struct tpm_chip *chip)
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{
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/* this causes the current command to be aborted */
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iowrite8(TPM_STS_COMMAND_READY,
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chip->vendor.iobase + TPM_STS(chip->vendor.locality));
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}
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static int get_burstcount(struct tpm_chip *chip)
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{
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unsigned long stop;
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int burstcnt;
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/* wait for burstcount */
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/* which timeout value, spec has 2 answers (c & d) */
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stop = jiffies + chip->vendor.timeout_d;
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do {
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burstcnt = ioread8(chip->vendor.iobase +
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TPM_STS(chip->vendor.locality) + 1);
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burstcnt += ioread8(chip->vendor.iobase +
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TPM_STS(chip->vendor.locality) +
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2) << 8;
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if (burstcnt)
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return burstcnt;
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msleep(TPM_TIMEOUT);
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} while (time_before(jiffies, stop));
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return -EBUSY;
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}
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static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
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{
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int size = 0, burstcnt;
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while (size < count &&
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wait_for_tpm_stat(chip,
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TPM_STS_DATA_AVAIL | TPM_STS_VALID,
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chip->vendor.timeout_c,
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&chip->vendor.read_queue, true)
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== 0) {
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burstcnt = get_burstcount(chip);
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for (; burstcnt > 0 && size < count; burstcnt--)
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buf[size++] = ioread8(chip->vendor.iobase +
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TPM_DATA_FIFO(chip->vendor.
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locality));
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}
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return size;
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}
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static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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{
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int size = 0;
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int expected, status;
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if (count < TPM_HEADER_SIZE) {
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size = -EIO;
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goto out;
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}
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/* read first 10 bytes, including tag, paramsize, and result */
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if ((size =
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recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
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dev_err(chip->pdev, "Unable to read header\n");
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goto out;
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}
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expected = be32_to_cpu(*(__be32 *) (buf + 2));
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if (expected > count) {
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size = -EIO;
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goto out;
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}
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if ((size +=
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recv_data(chip, &buf[TPM_HEADER_SIZE],
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expected - TPM_HEADER_SIZE)) < expected) {
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dev_err(chip->pdev, "Unable to read remainder of result\n");
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size = -ETIME;
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goto out;
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}
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wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
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&chip->vendor.int_queue, false);
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status = tpm_tis_status(chip);
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if (status & TPM_STS_DATA_AVAIL) { /* retry? */
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dev_err(chip->pdev, "Error left over data\n");
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size = -EIO;
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goto out;
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}
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out:
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tpm_tis_ready(chip);
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release_locality(chip, chip->vendor.locality, 0);
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return size;
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}
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static bool itpm;
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module_param(itpm, bool, 0444);
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MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)");
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/*
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* If interrupts are used (signaled by an irq set in the vendor structure)
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* tpm.c can skip polling for the data to be available as the interrupt is
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* waited for here
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*/
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static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
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{
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int rc, status, burstcnt;
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size_t count = 0;
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if (request_locality(chip, 0) < 0)
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return -EBUSY;
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status = tpm_tis_status(chip);
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if ((status & TPM_STS_COMMAND_READY) == 0) {
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tpm_tis_ready(chip);
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if (wait_for_tpm_stat
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(chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
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&chip->vendor.int_queue, false) < 0) {
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rc = -ETIME;
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goto out_err;
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}
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}
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while (count < len - 1) {
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burstcnt = get_burstcount(chip);
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for (; burstcnt > 0 && count < len - 1; burstcnt--) {
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iowrite8(buf[count], chip->vendor.iobase +
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TPM_DATA_FIFO(chip->vendor.locality));
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count++;
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}
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wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
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&chip->vendor.int_queue, false);
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status = tpm_tis_status(chip);
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if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
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rc = -EIO;
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goto out_err;
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}
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}
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/* write last byte */
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iowrite8(buf[count],
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chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality));
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wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
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&chip->vendor.int_queue, false);
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status = tpm_tis_status(chip);
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if ((status & TPM_STS_DATA_EXPECT) != 0) {
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rc = -EIO;
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goto out_err;
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}
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return 0;
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out_err:
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tpm_tis_ready(chip);
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release_locality(chip, chip->vendor.locality, 0);
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return rc;
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}
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static void disable_interrupts(struct tpm_chip *chip)
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{
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u32 intmask;
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intmask =
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ioread32(chip->vendor.iobase +
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TPM_INT_ENABLE(chip->vendor.locality));
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intmask &= ~TPM_GLOBAL_INT_ENABLE;
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iowrite32(intmask,
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chip->vendor.iobase +
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TPM_INT_ENABLE(chip->vendor.locality));
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free_irq(chip->vendor.irq, chip);
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chip->vendor.irq = 0;
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}
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/*
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* If interrupts are used (signaled by an irq set in the vendor structure)
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* tpm.c can skip polling for the data to be available as the interrupt is
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* waited for here
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*/
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static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len)
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{
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int rc;
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u32 ordinal;
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unsigned long dur;
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rc = tpm_tis_send_data(chip, buf, len);
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if (rc < 0)
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return rc;
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/* go and do it */
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iowrite8(TPM_STS_GO,
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chip->vendor.iobase + TPM_STS(chip->vendor.locality));
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if (chip->vendor.irq) {
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ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
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if (chip->flags & TPM_CHIP_FLAG_TPM2)
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dur = tpm2_calc_ordinal_duration(chip, ordinal);
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else
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dur = tpm_calc_ordinal_duration(chip, ordinal);
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if (wait_for_tpm_stat
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(chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur,
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&chip->vendor.read_queue, false) < 0) {
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rc = -ETIME;
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goto out_err;
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}
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}
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return len;
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out_err:
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tpm_tis_ready(chip);
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release_locality(chip, chip->vendor.locality, 0);
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return rc;
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}
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|
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static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
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{
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int rc, irq;
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struct priv_data *priv = chip->vendor.priv;
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if (!chip->vendor.irq || priv->irq_tested)
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return tpm_tis_send_main(chip, buf, len);
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|
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/* Verify receipt of the expected IRQ */
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irq = chip->vendor.irq;
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chip->vendor.irq = 0;
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rc = tpm_tis_send_main(chip, buf, len);
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chip->vendor.irq = irq;
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if (!priv->irq_tested)
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msleep(1);
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if (!priv->irq_tested) {
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disable_interrupts(chip);
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dev_err(chip->pdev,
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FW_BUG "TPM interrupt not working, polling instead\n");
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}
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priv->irq_tested = true;
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return rc;
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}
|
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|
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struct tis_vendor_timeout_override {
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u32 did_vid;
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unsigned long timeout_us[4];
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};
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|
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static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
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/* Atmel 3204 */
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{ 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000),
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(TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } },
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};
|
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|
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static bool tpm_tis_update_timeouts(struct tpm_chip *chip,
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unsigned long *timeout_cap)
|
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{
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int i;
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u32 did_vid;
|
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|
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did_vid = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
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|
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for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
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if (vendor_timeout_overrides[i].did_vid != did_vid)
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continue;
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memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us,
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sizeof(vendor_timeout_overrides[i].timeout_us));
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return true;
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}
|
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|
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return false;
|
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}
|
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|
|
/*
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* Early probing for iTPM with STS_DATA_EXPECT flaw.
|
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* Try sending command without itpm flag set and if that
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* fails, repeat with itpm flag set.
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*/
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static int probe_itpm(struct tpm_chip *chip)
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{
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int rc = 0;
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u8 cmd_getticks[] = {
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0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
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0x00, 0x00, 0x00, 0xf1
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};
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size_t len = sizeof(cmd_getticks);
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bool rem_itpm = itpm;
|
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u16 vendor = ioread16(chip->vendor.iobase + TPM_DID_VID(0));
|
|
|
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/* probe only iTPMS */
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if (vendor != TPM_VID_INTEL)
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return 0;
|
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|
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itpm = false;
|
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|
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rc = tpm_tis_send_data(chip, cmd_getticks, len);
|
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if (rc == 0)
|
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goto out;
|
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|
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tpm_tis_ready(chip);
|
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release_locality(chip, chip->vendor.locality, 0);
|
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|
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itpm = true;
|
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|
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rc = tpm_tis_send_data(chip, cmd_getticks, len);
|
|
if (rc == 0) {
|
|
dev_info(chip->pdev, "Detected an iTPM.\n");
|
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rc = 1;
|
|
} else
|
|
rc = -EFAULT;
|
|
|
|
out:
|
|
itpm = rem_itpm;
|
|
tpm_tis_ready(chip);
|
|
release_locality(chip, chip->vendor.locality, 0);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status)
|
|
{
|
|
switch (chip->vendor.manufacturer_id) {
|
|
case TPM_VID_WINBOND:
|
|
return ((status == TPM_STS_VALID) ||
|
|
(status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)));
|
|
case TPM_VID_STM:
|
|
return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY));
|
|
default:
|
|
return (status == TPM_STS_COMMAND_READY);
|
|
}
|
|
}
|
|
|
|
static const struct tpm_class_ops tpm_tis = {
|
|
.status = tpm_tis_status,
|
|
.recv = tpm_tis_recv,
|
|
.send = tpm_tis_send,
|
|
.cancel = tpm_tis_ready,
|
|
.update_timeouts = tpm_tis_update_timeouts,
|
|
.req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
|
|
.req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
|
|
.req_canceled = tpm_tis_req_canceled,
|
|
};
|
|
|
|
static irqreturn_t tis_int_probe(int irq, void *dev_id)
|
|
{
|
|
struct tpm_chip *chip = dev_id;
|
|
u32 interrupt;
|
|
|
|
interrupt = ioread32(chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality));
|
|
|
|
if (interrupt == 0)
|
|
return IRQ_NONE;
|
|
|
|
chip->vendor.probed_irq = irq;
|
|
|
|
/* Clear interrupts handled with TPM_EOI */
|
|
iowrite32(interrupt,
|
|
chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality));
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t tis_int_handler(int dummy, void *dev_id)
|
|
{
|
|
struct tpm_chip *chip = dev_id;
|
|
u32 interrupt;
|
|
int i;
|
|
|
|
interrupt = ioread32(chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality));
|
|
|
|
if (interrupt == 0)
|
|
return IRQ_NONE;
|
|
|
|
((struct priv_data *)chip->vendor.priv)->irq_tested = true;
|
|
if (interrupt & TPM_INTF_DATA_AVAIL_INT)
|
|
wake_up_interruptible(&chip->vendor.read_queue);
|
|
if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
|
|
for (i = 0; i < 5; i++)
|
|
if (check_locality(chip, i) >= 0)
|
|
break;
|
|
if (interrupt &
|
|
(TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
|
|
TPM_INTF_CMD_READY_INT))
|
|
wake_up_interruptible(&chip->vendor.int_queue);
|
|
|
|
/* Clear interrupts handled with TPM_EOI */
|
|
iowrite32(interrupt,
|
|
chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality));
|
|
ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static bool interrupts = true;
|
|
module_param(interrupts, bool, 0444);
|
|
MODULE_PARM_DESC(interrupts, "Enable interrupts");
|
|
|
|
static void tpm_tis_remove(struct tpm_chip *chip)
|
|
{
|
|
if (chip->flags & TPM_CHIP_FLAG_TPM2)
|
|
tpm2_shutdown(chip, TPM2_SU_CLEAR);
|
|
|
|
iowrite32(~TPM_GLOBAL_INT_ENABLE &
|
|
ioread32(chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.
|
|
locality)),
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
release_locality(chip, chip->vendor.locality, 1);
|
|
}
|
|
|
|
static int tpm_tis_init(struct device *dev, acpi_handle acpi_dev_handle,
|
|
resource_size_t start, resource_size_t len,
|
|
unsigned int irq)
|
|
{
|
|
u32 vendor, intfcaps, intmask;
|
|
int rc, i, irq_s, irq_e, probe;
|
|
struct tpm_chip *chip;
|
|
struct priv_data *priv;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL);
|
|
if (priv == NULL)
|
|
return -ENOMEM;
|
|
|
|
chip = tpmm_chip_alloc(dev, &tpm_tis);
|
|
if (IS_ERR(chip))
|
|
return PTR_ERR(chip);
|
|
|
|
chip->vendor.priv = priv;
|
|
#ifdef CONFIG_ACPI
|
|
chip->acpi_dev_handle = acpi_dev_handle;
|
|
#endif
|
|
|
|
chip->vendor.iobase = devm_ioremap(dev, start, len);
|
|
if (!chip->vendor.iobase)
|
|
return -EIO;
|
|
|
|
/* Maximum timeouts */
|
|
chip->vendor.timeout_a = TIS_TIMEOUT_A_MAX;
|
|
chip->vendor.timeout_b = TIS_TIMEOUT_B_MAX;
|
|
chip->vendor.timeout_c = TIS_TIMEOUT_C_MAX;
|
|
chip->vendor.timeout_d = TIS_TIMEOUT_D_MAX;
|
|
|
|
if (wait_startup(chip, 0) != 0) {
|
|
rc = -ENODEV;
|
|
goto out_err;
|
|
}
|
|
|
|
if (request_locality(chip, 0) != 0) {
|
|
rc = -ENODEV;
|
|
goto out_err;
|
|
}
|
|
|
|
rc = tpm2_probe(chip);
|
|
if (rc)
|
|
goto out_err;
|
|
|
|
vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
|
|
chip->vendor.manufacturer_id = vendor;
|
|
|
|
dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n",
|
|
(chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
|
|
vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
|
|
|
|
if (!itpm) {
|
|
probe = probe_itpm(chip);
|
|
if (probe < 0) {
|
|
rc = -ENODEV;
|
|
goto out_err;
|
|
}
|
|
itpm = !!probe;
|
|
}
|
|
|
|
if (itpm)
|
|
dev_info(dev, "Intel iTPM workaround enabled\n");
|
|
|
|
|
|
/* Figure out the capabilities */
|
|
intfcaps =
|
|
ioread32(chip->vendor.iobase +
|
|
TPM_INTF_CAPS(chip->vendor.locality));
|
|
dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
|
|
intfcaps);
|
|
if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
|
|
dev_dbg(dev, "\tBurst Count Static\n");
|
|
if (intfcaps & TPM_INTF_CMD_READY_INT)
|
|
dev_dbg(dev, "\tCommand Ready Int Support\n");
|
|
if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
|
|
dev_dbg(dev, "\tInterrupt Edge Falling\n");
|
|
if (intfcaps & TPM_INTF_INT_EDGE_RISING)
|
|
dev_dbg(dev, "\tInterrupt Edge Rising\n");
|
|
if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
|
|
dev_dbg(dev, "\tInterrupt Level Low\n");
|
|
if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
|
|
dev_dbg(dev, "\tInterrupt Level High\n");
|
|
if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
|
|
dev_dbg(dev, "\tLocality Change Int Support\n");
|
|
if (intfcaps & TPM_INTF_STS_VALID_INT)
|
|
dev_dbg(dev, "\tSts Valid Int Support\n");
|
|
if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
|
|
dev_dbg(dev, "\tData Avail Int Support\n");
|
|
|
|
/* INTERRUPT Setup */
|
|
init_waitqueue_head(&chip->vendor.read_queue);
|
|
init_waitqueue_head(&chip->vendor.int_queue);
|
|
|
|
intmask =
|
|
ioread32(chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
|
|
intmask |= TPM_INTF_CMD_READY_INT
|
|
| TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
|
|
| TPM_INTF_STS_VALID_INT;
|
|
|
|
iowrite32(intmask,
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
if (interrupts)
|
|
chip->vendor.irq = irq;
|
|
if (interrupts && !chip->vendor.irq) {
|
|
irq_s =
|
|
ioread8(chip->vendor.iobase +
|
|
TPM_INT_VECTOR(chip->vendor.locality));
|
|
if (irq_s) {
|
|
irq_e = irq_s;
|
|
} else {
|
|
irq_s = 3;
|
|
irq_e = 15;
|
|
}
|
|
|
|
for (i = irq_s; i <= irq_e && chip->vendor.irq == 0; i++) {
|
|
iowrite8(i, chip->vendor.iobase +
|
|
TPM_INT_VECTOR(chip->vendor.locality));
|
|
if (devm_request_irq
|
|
(dev, i, tis_int_probe, IRQF_SHARED,
|
|
chip->devname, chip) != 0) {
|
|
dev_info(chip->pdev,
|
|
"Unable to request irq: %d for probe\n",
|
|
i);
|
|
continue;
|
|
}
|
|
|
|
/* Clear all existing */
|
|
iowrite32(ioread32
|
|
(chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality)),
|
|
chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality));
|
|
|
|
/* Turn on */
|
|
iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
|
|
chip->vendor.probed_irq = 0;
|
|
|
|
/* Generate Interrupts */
|
|
if (chip->flags & TPM_CHIP_FLAG_TPM2)
|
|
tpm2_gen_interrupt(chip);
|
|
else
|
|
tpm_gen_interrupt(chip);
|
|
|
|
chip->vendor.irq = chip->vendor.probed_irq;
|
|
|
|
/* free_irq will call into tis_int_probe;
|
|
clear all irqs we haven't seen while doing
|
|
tpm_gen_interrupt */
|
|
iowrite32(ioread32
|
|
(chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality)),
|
|
chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality));
|
|
|
|
/* Turn off */
|
|
iowrite32(intmask,
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
}
|
|
}
|
|
if (chip->vendor.irq) {
|
|
iowrite8(chip->vendor.irq,
|
|
chip->vendor.iobase +
|
|
TPM_INT_VECTOR(chip->vendor.locality));
|
|
if (devm_request_irq
|
|
(dev, chip->vendor.irq, tis_int_handler, IRQF_SHARED,
|
|
chip->devname, chip) != 0) {
|
|
dev_info(chip->pdev,
|
|
"Unable to request irq: %d for use\n",
|
|
chip->vendor.irq);
|
|
chip->vendor.irq = 0;
|
|
} else {
|
|
/* Clear all existing */
|
|
iowrite32(ioread32
|
|
(chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality)),
|
|
chip->vendor.iobase +
|
|
TPM_INT_STATUS(chip->vendor.locality));
|
|
|
|
/* Turn on */
|
|
iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
|
|
chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
}
|
|
}
|
|
|
|
if (chip->flags & TPM_CHIP_FLAG_TPM2) {
|
|
chip->vendor.timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
|
|
chip->vendor.timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
|
|
chip->vendor.timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
|
|
chip->vendor.timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
|
|
chip->vendor.duration[TPM_SHORT] =
|
|
msecs_to_jiffies(TPM2_DURATION_SHORT);
|
|
chip->vendor.duration[TPM_MEDIUM] =
|
|
msecs_to_jiffies(TPM2_DURATION_MEDIUM);
|
|
chip->vendor.duration[TPM_LONG] =
|
|
msecs_to_jiffies(TPM2_DURATION_LONG);
|
|
|
|
rc = tpm2_do_selftest(chip);
|
|
if (rc == TPM2_RC_INITIALIZE) {
|
|
dev_warn(dev, "Firmware has not started TPM\n");
|
|
rc = tpm2_startup(chip, TPM2_SU_CLEAR);
|
|
if (!rc)
|
|
rc = tpm2_do_selftest(chip);
|
|
}
|
|
|
|
if (rc) {
|
|
dev_err(dev, "TPM self test failed\n");
|
|
if (rc > 0)
|
|
rc = -ENODEV;
|
|
goto out_err;
|
|
}
|
|
} else {
|
|
if (tpm_get_timeouts(chip)) {
|
|
dev_err(dev, "Could not get TPM timeouts and durations\n");
|
|
rc = -ENODEV;
|
|
goto out_err;
|
|
}
|
|
|
|
if (tpm_do_selftest(chip)) {
|
|
dev_err(dev, "TPM self test failed\n");
|
|
rc = -ENODEV;
|
|
goto out_err;
|
|
}
|
|
}
|
|
|
|
return tpm_chip_register(chip);
|
|
out_err:
|
|
tpm_tis_remove(chip);
|
|
return rc;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
|
|
{
|
|
u32 intmask;
|
|
|
|
/* reenable interrupts that device may have lost or
|
|
BIOS/firmware may have disabled */
|
|
iowrite8(chip->vendor.irq, chip->vendor.iobase +
|
|
TPM_INT_VECTOR(chip->vendor.locality));
|
|
|
|
intmask =
|
|
ioread32(chip->vendor.iobase +
|
|
TPM_INT_ENABLE(chip->vendor.locality));
|
|
|
|
intmask |= TPM_INTF_CMD_READY_INT
|
|
| TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
|
|
| TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
|
|
|
|
iowrite32(intmask,
|
|
chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
|
|
}
|
|
|
|
static int tpm_tis_resume(struct device *dev)
|
|
{
|
|
struct tpm_chip *chip = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
if (chip->vendor.irq)
|
|
tpm_tis_reenable_interrupts(chip);
|
|
|
|
ret = tpm_pm_resume(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* TPM 1.2 requires self-test on resume. This function actually returns
|
|
* an error code but for unknown reason it isn't handled.
|
|
*/
|
|
if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
|
|
tpm_do_selftest(chip);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
|
|
|
|
#ifdef CONFIG_PNP
|
|
static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
|
|
const struct pnp_device_id *pnp_id)
|
|
{
|
|
resource_size_t start, len;
|
|
unsigned int irq = 0;
|
|
acpi_handle acpi_dev_handle = NULL;
|
|
|
|
start = pnp_mem_start(pnp_dev, 0);
|
|
len = pnp_mem_len(pnp_dev, 0);
|
|
|
|
if (pnp_irq_valid(pnp_dev, 0))
|
|
irq = pnp_irq(pnp_dev, 0);
|
|
else
|
|
interrupts = false;
|
|
|
|
if (is_itpm(pnp_dev))
|
|
itpm = true;
|
|
|
|
#ifdef CONFIG_ACPI
|
|
if (pnp_acpi_device(pnp_dev))
|
|
acpi_dev_handle = pnp_acpi_device(pnp_dev)->handle;
|
|
#endif
|
|
|
|
return tpm_tis_init(&pnp_dev->dev, acpi_dev_handle, start, len, irq);
|
|
}
|
|
|
|
static struct pnp_device_id tpm_pnp_tbl[] = {
|
|
{"PNP0C31", 0}, /* TPM */
|
|
{"ATM1200", 0}, /* Atmel */
|
|
{"IFX0102", 0}, /* Infineon */
|
|
{"BCM0101", 0}, /* Broadcom */
|
|
{"BCM0102", 0}, /* Broadcom */
|
|
{"NSC1200", 0}, /* National */
|
|
{"ICO0102", 0}, /* Intel */
|
|
/* Add new here */
|
|
{"", 0}, /* User Specified */
|
|
{"", 0} /* Terminator */
|
|
};
|
|
MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl);
|
|
|
|
static void tpm_tis_pnp_remove(struct pnp_dev *dev)
|
|
{
|
|
struct tpm_chip *chip = pnp_get_drvdata(dev);
|
|
tpm_chip_unregister(chip);
|
|
tpm_tis_remove(chip);
|
|
}
|
|
|
|
static struct pnp_driver tis_pnp_driver = {
|
|
.name = "tpm_tis",
|
|
.id_table = tpm_pnp_tbl,
|
|
.probe = tpm_tis_pnp_init,
|
|
.remove = tpm_tis_pnp_remove,
|
|
.driver = {
|
|
.pm = &tpm_tis_pm,
|
|
},
|
|
};
|
|
|
|
#define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2
|
|
module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id,
|
|
sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444);
|
|
MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe");
|
|
#endif
|
|
|
|
static struct platform_driver tis_drv = {
|
|
.driver = {
|
|
.name = "tpm_tis",
|
|
.pm = &tpm_tis_pm,
|
|
},
|
|
};
|
|
|
|
static struct platform_device *pdev;
|
|
|
|
static bool force;
|
|
module_param(force, bool, 0444);
|
|
MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry");
|
|
static int __init init_tis(void)
|
|
{
|
|
int rc;
|
|
#ifdef CONFIG_PNP
|
|
if (!force)
|
|
return pnp_register_driver(&tis_pnp_driver);
|
|
#endif
|
|
|
|
rc = platform_driver_register(&tis_drv);
|
|
if (rc < 0)
|
|
return rc;
|
|
pdev = platform_device_register_simple("tpm_tis", -1, NULL, 0);
|
|
if (IS_ERR(pdev)) {
|
|
rc = PTR_ERR(pdev);
|
|
goto err_dev;
|
|
}
|
|
rc = tpm_tis_init(&pdev->dev, NULL, TIS_MEM_BASE, TIS_MEM_LEN, 0);
|
|
if (rc)
|
|
goto err_init;
|
|
return 0;
|
|
err_init:
|
|
platform_device_unregister(pdev);
|
|
err_dev:
|
|
platform_driver_unregister(&tis_drv);
|
|
return rc;
|
|
}
|
|
|
|
static void __exit cleanup_tis(void)
|
|
{
|
|
struct tpm_chip *chip;
|
|
#ifdef CONFIG_PNP
|
|
if (!force) {
|
|
pnp_unregister_driver(&tis_pnp_driver);
|
|
return;
|
|
}
|
|
#endif
|
|
chip = dev_get_drvdata(&pdev->dev);
|
|
tpm_chip_unregister(chip);
|
|
tpm_tis_remove(chip);
|
|
platform_device_unregister(pdev);
|
|
platform_driver_unregister(&tis_drv);
|
|
}
|
|
|
|
module_init(init_tis);
|
|
module_exit(cleanup_tis);
|
|
MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
|
|
MODULE_DESCRIPTION("TPM Driver");
|
|
MODULE_VERSION("2.0");
|
|
MODULE_LICENSE("GPL");
|