1709 lines
41 KiB
C
1709 lines
41 KiB
C
/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
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*
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* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* Thanks to the following companies for their support:
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*
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* - JMicron (hardware and technical support)
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*/
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#include <linux/delay.h>
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#include <linux/highmem.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/mmc/host.h>
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#include <linux/scatterlist.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/pm_runtime.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/mmc/sdhci-pci-data.h>
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#include "sdhci.h"
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#include "sdhci-pci.h"
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#include "sdhci-pci-o2micro.h"
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/*****************************************************************************\
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* *
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* Hardware specific quirk handling *
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* *
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\*****************************************************************************/
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static int ricoh_probe(struct sdhci_pci_chip *chip)
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{
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if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
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chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
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chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
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return 0;
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}
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static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->caps =
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((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
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& SDHCI_TIMEOUT_CLK_MASK) |
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((0x21 << SDHCI_CLOCK_BASE_SHIFT)
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& SDHCI_CLOCK_BASE_MASK) |
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SDHCI_TIMEOUT_CLK_UNIT |
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SDHCI_CAN_VDD_330 |
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SDHCI_CAN_DO_HISPD |
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SDHCI_CAN_DO_SDMA;
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return 0;
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}
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static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
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{
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/* Apply a delay to allow controller to settle */
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/* Otherwise it becomes confused if card state changed
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during suspend */
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msleep(500);
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return 0;
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}
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static const struct sdhci_pci_fixes sdhci_ricoh = {
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.probe = ricoh_probe,
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.quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_FORCE_DMA |
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SDHCI_QUIRK_CLOCK_BEFORE_RESET,
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};
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static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
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.probe_slot = ricoh_mmc_probe_slot,
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.resume = ricoh_mmc_resume,
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.quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_CLOCK_BEFORE_RESET |
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SDHCI_QUIRK_NO_CARD_NO_RESET |
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SDHCI_QUIRK_MISSING_CAPS
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};
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static const struct sdhci_pci_fixes sdhci_ene_712 = {
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.quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
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SDHCI_QUIRK_BROKEN_DMA,
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};
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static const struct sdhci_pci_fixes sdhci_ene_714 = {
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.quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
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SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
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SDHCI_QUIRK_BROKEN_DMA,
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};
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static const struct sdhci_pci_fixes sdhci_cafe = {
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.quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
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SDHCI_QUIRK_NO_BUSY_IRQ |
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SDHCI_QUIRK_BROKEN_CARD_DETECTION |
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SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
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};
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static const struct sdhci_pci_fixes sdhci_intel_qrk = {
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.quirks = SDHCI_QUIRK_NO_HISPD_BIT,
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};
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static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
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return 0;
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}
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/*
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* ADMA operation is disabled for Moorestown platform due to
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* hardware bugs.
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*/
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static int mrst_hc_probe(struct sdhci_pci_chip *chip)
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{
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/*
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* slots number is fixed here for MRST as SDIO3/5 are never used and
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* have hardware bugs.
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*/
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chip->num_slots = 1;
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return 0;
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}
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static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
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return 0;
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}
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#ifdef CONFIG_PM
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static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
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{
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struct sdhci_pci_slot *slot = dev_id;
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struct sdhci_host *host = slot->host;
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mmc_detect_change(host->mmc, msecs_to_jiffies(200));
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return IRQ_HANDLED;
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}
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static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
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{
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int err, irq, gpio = slot->cd_gpio;
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slot->cd_gpio = -EINVAL;
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slot->cd_irq = -EINVAL;
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if (!gpio_is_valid(gpio))
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return;
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err = gpio_request(gpio, "sd_cd");
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if (err < 0)
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goto out;
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err = gpio_direction_input(gpio);
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if (err < 0)
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goto out_free;
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irq = gpio_to_irq(gpio);
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if (irq < 0)
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goto out_free;
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err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
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IRQF_TRIGGER_FALLING, "sd_cd", slot);
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if (err)
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goto out_free;
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slot->cd_gpio = gpio;
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slot->cd_irq = irq;
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return;
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out_free:
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gpio_free(gpio);
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out:
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dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
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}
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static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
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{
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if (slot->cd_irq >= 0)
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free_irq(slot->cd_irq, slot);
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if (gpio_is_valid(slot->cd_gpio))
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gpio_free(slot->cd_gpio);
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}
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#else
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static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
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{
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}
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static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
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{
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}
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#endif
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static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
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slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
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MMC_CAP2_HC_ERASE_SZ;
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return 0;
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}
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static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
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return 0;
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}
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static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
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.quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
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.probe_slot = mrst_hc_probe_slot,
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};
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static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
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.quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
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.probe = mrst_hc_probe,
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};
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static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.allow_runtime_pm = true,
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.own_cd_for_runtime_pm = true,
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};
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static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
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.allow_runtime_pm = true,
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.probe_slot = mfd_sdio_probe_slot,
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};
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static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.allow_runtime_pm = true,
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.probe_slot = mfd_emmc_probe_slot,
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};
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static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
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.quirks = SDHCI_QUIRK_BROKEN_ADMA,
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.probe_slot = pch_hc_probe_slot,
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};
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static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
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{
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u8 reg;
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reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
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reg |= 0x10;
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sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
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/* For eMMC, minimum is 1us but give it 9us for good measure */
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udelay(9);
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reg &= ~0x10;
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sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
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/* For eMMC, minimum is 200us but give it 300us for good measure */
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usleep_range(300, 1000);
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}
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static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
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MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
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MMC_CAP_BUS_WIDTH_TEST |
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MMC_CAP_WAIT_WHILE_BUSY;
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slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
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slot->hw_reset = sdhci_pci_int_hw_reset;
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if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
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slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
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return 0;
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}
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static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
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MMC_CAP_BUS_WIDTH_TEST |
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MMC_CAP_WAIT_WHILE_BUSY;
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return 0;
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}
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static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
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{
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slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
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MMC_CAP_WAIT_WHILE_BUSY;
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slot->cd_con_id = NULL;
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slot->cd_idx = 0;
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slot->cd_override_level = true;
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return 0;
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}
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static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
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.allow_runtime_pm = true,
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.probe_slot = byt_emmc_probe_slot,
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_STOP_WITH_TC,
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};
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static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
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SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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.allow_runtime_pm = true,
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.probe_slot = byt_sdio_probe_slot,
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};
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static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
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SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_STOP_WITH_TC,
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.allow_runtime_pm = true,
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.own_cd_for_runtime_pm = true,
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.probe_slot = byt_sd_probe_slot,
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};
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/* Define Host controllers for Intel Merrifield platform */
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#define INTEL_MRFL_EMMC_0 0
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#define INTEL_MRFL_EMMC_1 1
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static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
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{
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if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
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(PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
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/* SD support is not ready yet */
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return -ENODEV;
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slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
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MMC_CAP_1_8V_DDR;
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return 0;
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}
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static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
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.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
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.quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
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SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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.allow_runtime_pm = true,
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.probe_slot = intel_mrfl_mmc_probe_slot,
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};
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/* O2Micro extra registers */
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#define O2_SD_LOCK_WP 0xD3
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#define O2_SD_MULTI_VCC3V 0xEE
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#define O2_SD_CLKREQ 0xEC
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#define O2_SD_CAPS 0xE0
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#define O2_SD_ADMA1 0xE2
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#define O2_SD_ADMA2 0xE7
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#define O2_SD_INF_MOD 0xF1
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static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
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{
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u8 scratch;
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int ret;
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ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
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if (ret)
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return ret;
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/*
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* Turn PMOS on [bit 0], set over current detection to 2.4 V
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* [bit 1:2] and enable over current debouncing [bit 6].
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*/
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if (on)
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scratch |= 0x47;
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else
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scratch &= ~0x47;
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ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
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if (ret)
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return ret;
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return 0;
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}
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static int jmicron_probe(struct sdhci_pci_chip *chip)
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{
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int ret;
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u16 mmcdev = 0;
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if (chip->pdev->revision == 0) {
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chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
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SDHCI_QUIRK_32BIT_DMA_SIZE |
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SDHCI_QUIRK_32BIT_ADMA_SIZE |
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SDHCI_QUIRK_RESET_AFTER_REQUEST |
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SDHCI_QUIRK_BROKEN_SMALL_PIO;
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}
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/*
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* JMicron chips can have two interfaces to the same hardware
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* in order to work around limitations in Microsoft's driver.
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* We need to make sure we only bind to one of them.
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*
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* This code assumes two things:
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*
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* 1. The PCI code adds subfunctions in order.
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*
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* 2. The MMC interface has a lower subfunction number
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* than the SD interface.
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*/
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if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
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mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
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else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
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mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
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if (mmcdev) {
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struct pci_dev *sd_dev;
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sd_dev = NULL;
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while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
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mmcdev, sd_dev)) != NULL) {
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if ((PCI_SLOT(chip->pdev->devfn) ==
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PCI_SLOT(sd_dev->devfn)) &&
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(chip->pdev->bus == sd_dev->bus))
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break;
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}
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if (sd_dev) {
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pci_dev_put(sd_dev);
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dev_info(&chip->pdev->dev, "Refusing to bind to "
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"secondary interface.\n");
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return -ENODEV;
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}
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}
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/*
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* JMicron chips need a bit of a nudge to enable the power
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* output pins.
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*/
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ret = jmicron_pmos(chip, 1);
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if (ret) {
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dev_err(&chip->pdev->dev, "Failure enabling card power\n");
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return ret;
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}
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/* quirk for unsable RO-detection on JM388 chips */
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if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
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chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
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chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
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return 0;
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}
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static void jmicron_enable_mmc(struct sdhci_host *host, int on)
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{
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u8 scratch;
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scratch = readb(host->ioaddr + 0xC0);
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if (on)
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scratch |= 0x01;
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else
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scratch &= ~0x01;
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writeb(scratch, host->ioaddr + 0xC0);
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}
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static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
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{
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if (slot->chip->pdev->revision == 0) {
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u16 version;
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version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
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version = (version & SDHCI_VENDOR_VER_MASK) >>
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SDHCI_VENDOR_VER_SHIFT;
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/*
|
|
* Older versions of the chip have lots of nasty glitches
|
|
* in the ADMA engine. It's best just to avoid it
|
|
* completely.
|
|
*/
|
|
if (version < 0xAC)
|
|
slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
|
|
}
|
|
|
|
/* JM388 MMC doesn't support 1.8V while SD supports it */
|
|
if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
|
|
slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
|
|
MMC_VDD_29_30 | MMC_VDD_30_31 |
|
|
MMC_VDD_165_195; /* allow 1.8V */
|
|
slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
|
|
MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
|
|
}
|
|
|
|
/*
|
|
* The secondary interface requires a bit set to get the
|
|
* interrupts.
|
|
*/
|
|
if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
|
|
slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
|
|
jmicron_enable_mmc(slot->host, 1);
|
|
|
|
slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
|
|
{
|
|
if (dead)
|
|
return;
|
|
|
|
if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
|
|
slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
|
|
jmicron_enable_mmc(slot->host, 0);
|
|
}
|
|
|
|
static int jmicron_suspend(struct sdhci_pci_chip *chip)
|
|
{
|
|
int i;
|
|
|
|
if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
|
|
chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
|
|
for (i = 0; i < chip->num_slots; i++)
|
|
jmicron_enable_mmc(chip->slots[i]->host, 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int jmicron_resume(struct sdhci_pci_chip *chip)
|
|
{
|
|
int ret, i;
|
|
|
|
if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
|
|
chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
|
|
for (i = 0; i < chip->num_slots; i++)
|
|
jmicron_enable_mmc(chip->slots[i]->host, 1);
|
|
}
|
|
|
|
ret = jmicron_pmos(chip, 1);
|
|
if (ret) {
|
|
dev_err(&chip->pdev->dev, "Failure enabling card power\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct sdhci_pci_fixes sdhci_o2 = {
|
|
.probe = sdhci_pci_o2_probe,
|
|
.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
|
|
.probe_slot = sdhci_pci_o2_probe_slot,
|
|
.resume = sdhci_pci_o2_resume,
|
|
};
|
|
|
|
static const struct sdhci_pci_fixes sdhci_jmicron = {
|
|
.probe = jmicron_probe,
|
|
|
|
.probe_slot = jmicron_probe_slot,
|
|
.remove_slot = jmicron_remove_slot,
|
|
|
|
.suspend = jmicron_suspend,
|
|
.resume = jmicron_resume,
|
|
};
|
|
|
|
/* SysKonnect CardBus2SDIO extra registers */
|
|
#define SYSKT_CTRL 0x200
|
|
#define SYSKT_RDFIFO_STAT 0x204
|
|
#define SYSKT_WRFIFO_STAT 0x208
|
|
#define SYSKT_POWER_DATA 0x20c
|
|
#define SYSKT_POWER_330 0xef
|
|
#define SYSKT_POWER_300 0xf8
|
|
#define SYSKT_POWER_184 0xcc
|
|
#define SYSKT_POWER_CMD 0x20d
|
|
#define SYSKT_POWER_START (1 << 7)
|
|
#define SYSKT_POWER_STATUS 0x20e
|
|
#define SYSKT_POWER_STATUS_OK (1 << 0)
|
|
#define SYSKT_BOARD_REV 0x210
|
|
#define SYSKT_CHIP_REV 0x211
|
|
#define SYSKT_CONF_DATA 0x212
|
|
#define SYSKT_CONF_DATA_1V8 (1 << 2)
|
|
#define SYSKT_CONF_DATA_2V5 (1 << 1)
|
|
#define SYSKT_CONF_DATA_3V3 (1 << 0)
|
|
|
|
static int syskt_probe(struct sdhci_pci_chip *chip)
|
|
{
|
|
if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
|
|
chip->pdev->class &= ~0x0000FF;
|
|
chip->pdev->class |= PCI_SDHCI_IFDMA;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int syskt_probe_slot(struct sdhci_pci_slot *slot)
|
|
{
|
|
int tm, ps;
|
|
|
|
u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
|
|
u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
|
|
dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
|
|
"board rev %d.%d, chip rev %d.%d\n",
|
|
board_rev >> 4, board_rev & 0xf,
|
|
chip_rev >> 4, chip_rev & 0xf);
|
|
if (chip_rev >= 0x20)
|
|
slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
|
|
|
|
writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
|
|
writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
|
|
udelay(50);
|
|
tm = 10; /* Wait max 1 ms */
|
|
do {
|
|
ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
|
|
if (ps & SYSKT_POWER_STATUS_OK)
|
|
break;
|
|
udelay(100);
|
|
} while (--tm);
|
|
if (!tm) {
|
|
dev_err(&slot->chip->pdev->dev,
|
|
"power regulator never stabilized");
|
|
writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct sdhci_pci_fixes sdhci_syskt = {
|
|
.quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
|
|
.probe = syskt_probe,
|
|
.probe_slot = syskt_probe_slot,
|
|
};
|
|
|
|
static int via_probe(struct sdhci_pci_chip *chip)
|
|
{
|
|
if (chip->pdev->revision == 0x10)
|
|
chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct sdhci_pci_fixes sdhci_via = {
|
|
.probe = via_probe,
|
|
};
|
|
|
|
static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
|
|
{
|
|
slot->host->mmc->caps2 |= MMC_CAP2_HS200;
|
|
return 0;
|
|
}
|
|
|
|
static const struct sdhci_pci_fixes sdhci_rtsx = {
|
|
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
|
|
SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
|
|
SDHCI_QUIRK2_BROKEN_DDR50,
|
|
.probe_slot = rtsx_probe_slot,
|
|
};
|
|
|
|
static int amd_probe(struct sdhci_pci_chip *chip)
|
|
{
|
|
struct pci_dev *smbus_dev;
|
|
|
|
smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
|
|
PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
|
|
|
|
if (smbus_dev && (smbus_dev->revision < 0x51)) {
|
|
chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
|
|
chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct sdhci_pci_fixes sdhci_amd = {
|
|
.probe = amd_probe,
|
|
};
|
|
|
|
static const struct pci_device_id pci_ids[] = {
|
|
{
|
|
.vendor = PCI_VENDOR_ID_RICOH,
|
|
.device = PCI_DEVICE_ID_RICOH_R5C822,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_ricoh,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_RICOH,
|
|
.device = 0x843,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_RICOH,
|
|
.device = 0xe822,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_RICOH,
|
|
.device = 0xe823,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_ENE,
|
|
.device = PCI_DEVICE_ID_ENE_CB712_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_ene_712,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_ENE,
|
|
.device = PCI_DEVICE_ID_ENE_CB712_SD_2,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_ene_712,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_ENE,
|
|
.device = PCI_DEVICE_ID_ENE_CB714_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_ene_714,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_ENE,
|
|
.device = PCI_DEVICE_ID_ENE_CB714_SD_2,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_ene_714,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_MARVELL,
|
|
.device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_cafe,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_JMICRON,
|
|
.device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_jmicron,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_JMICRON,
|
|
.device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_jmicron,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_JMICRON,
|
|
.device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_jmicron,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_JMICRON,
|
|
.device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_jmicron,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_SYSKONNECT,
|
|
.device = 0x8000,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_syskt,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_VIA,
|
|
.device = 0x95d0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_via,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_REALTEK,
|
|
.device = 0x5250,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_rtsx,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_QRK_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_MRST_SD0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_MRST_SD1,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_MRST_SD2,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_MFD_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_BYT_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_BSW_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.device = PCI_DEVICE_ID_INTEL_SPT_SD,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_8120,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_8220,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_8221,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_8320,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_8321,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_FUJIN2,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_SDS0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_SDS1,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_SEABIRD0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
|
|
{
|
|
.vendor = PCI_VENDOR_ID_O2,
|
|
.device = PCI_DEVICE_ID_O2_SEABIRD1,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
|
},
|
|
{
|
|
.vendor = PCI_VENDOR_ID_AMD,
|
|
.device = PCI_ANY_ID,
|
|
.class = PCI_CLASS_SYSTEM_SDHCI << 8,
|
|
.class_mask = 0xFFFF00,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
.driver_data = (kernel_ulong_t)&sdhci_amd,
|
|
},
|
|
{ /* Generic SD host controller */
|
|
PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
|
|
},
|
|
|
|
{ /* end: all zeroes */ },
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, pci_ids);
|
|
|
|
/*****************************************************************************\
|
|
* *
|
|
* SDHCI core callbacks *
|
|
* *
|
|
\*****************************************************************************/
|
|
|
|
static int sdhci_pci_enable_dma(struct sdhci_host *host)
|
|
{
|
|
struct sdhci_pci_slot *slot;
|
|
struct pci_dev *pdev;
|
|
int ret = -1;
|
|
|
|
slot = sdhci_priv(host);
|
|
pdev = slot->chip->pdev;
|
|
|
|
if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
|
|
((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
|
|
(host->flags & SDHCI_USE_SDMA)) {
|
|
dev_warn(&pdev->dev, "Will use DMA mode even though HW "
|
|
"doesn't fully claim to support it.\n");
|
|
}
|
|
|
|
if (host->flags & SDHCI_USE_64_BIT_DMA) {
|
|
if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
|
|
host->flags &= ~SDHCI_USE_64_BIT_DMA;
|
|
} else {
|
|
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
|
|
if (ret)
|
|
dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
|
|
}
|
|
}
|
|
if (ret)
|
|
ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
|
if (ret)
|
|
return ret;
|
|
|
|
pci_set_master(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
|
|
{
|
|
u8 ctrl;
|
|
|
|
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
|
|
|
|
switch (width) {
|
|
case MMC_BUS_WIDTH_8:
|
|
ctrl |= SDHCI_CTRL_8BITBUS;
|
|
ctrl &= ~SDHCI_CTRL_4BITBUS;
|
|
break;
|
|
case MMC_BUS_WIDTH_4:
|
|
ctrl |= SDHCI_CTRL_4BITBUS;
|
|
ctrl &= ~SDHCI_CTRL_8BITBUS;
|
|
break;
|
|
default:
|
|
ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
|
|
break;
|
|
}
|
|
|
|
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
|
|
}
|
|
|
|
static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
|
|
{
|
|
struct sdhci_pci_slot *slot = sdhci_priv(host);
|
|
int rst_n_gpio = slot->rst_n_gpio;
|
|
|
|
if (!gpio_is_valid(rst_n_gpio))
|
|
return;
|
|
gpio_set_value_cansleep(rst_n_gpio, 0);
|
|
/* For eMMC, minimum is 1us but give it 10us for good measure */
|
|
udelay(10);
|
|
gpio_set_value_cansleep(rst_n_gpio, 1);
|
|
/* For eMMC, minimum is 200us but give it 300us for good measure */
|
|
usleep_range(300, 1000);
|
|
}
|
|
|
|
static void sdhci_pci_hw_reset(struct sdhci_host *host)
|
|
{
|
|
struct sdhci_pci_slot *slot = sdhci_priv(host);
|
|
|
|
if (slot->hw_reset)
|
|
slot->hw_reset(host);
|
|
}
|
|
|
|
static const struct sdhci_ops sdhci_pci_ops = {
|
|
.set_clock = sdhci_set_clock,
|
|
.enable_dma = sdhci_pci_enable_dma,
|
|
.set_bus_width = sdhci_pci_set_bus_width,
|
|
.reset = sdhci_reset,
|
|
.set_uhs_signaling = sdhci_set_uhs_signaling,
|
|
.hw_reset = sdhci_pci_hw_reset,
|
|
};
|
|
|
|
/*****************************************************************************\
|
|
* *
|
|
* Suspend/resume *
|
|
* *
|
|
\*****************************************************************************/
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int sdhci_pci_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct sdhci_pci_chip *chip;
|
|
struct sdhci_pci_slot *slot;
|
|
mmc_pm_flag_t slot_pm_flags;
|
|
mmc_pm_flag_t pm_flags = 0;
|
|
int i, ret;
|
|
|
|
chip = pci_get_drvdata(pdev);
|
|
if (!chip)
|
|
return 0;
|
|
|
|
for (i = 0; i < chip->num_slots; i++) {
|
|
slot = chip->slots[i];
|
|
if (!slot)
|
|
continue;
|
|
|
|
ret = sdhci_suspend_host(slot->host);
|
|
|
|
if (ret)
|
|
goto err_pci_suspend;
|
|
|
|
slot_pm_flags = slot->host->mmc->pm_flags;
|
|
if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
|
|
sdhci_enable_irq_wakeups(slot->host);
|
|
|
|
pm_flags |= slot_pm_flags;
|
|
}
|
|
|
|
if (chip->fixes && chip->fixes->suspend) {
|
|
ret = chip->fixes->suspend(chip);
|
|
if (ret)
|
|
goto err_pci_suspend;
|
|
}
|
|
|
|
if (pm_flags & MMC_PM_KEEP_POWER) {
|
|
if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
|
|
device_init_wakeup(dev, true);
|
|
else
|
|
device_init_wakeup(dev, false);
|
|
} else
|
|
device_init_wakeup(dev, false);
|
|
|
|
return 0;
|
|
|
|
err_pci_suspend:
|
|
while (--i >= 0)
|
|
sdhci_resume_host(chip->slots[i]->host);
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_pci_resume(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct sdhci_pci_chip *chip;
|
|
struct sdhci_pci_slot *slot;
|
|
int i, ret;
|
|
|
|
chip = pci_get_drvdata(pdev);
|
|
if (!chip)
|
|
return 0;
|
|
|
|
if (chip->fixes && chip->fixes->resume) {
|
|
ret = chip->fixes->resume(chip);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < chip->num_slots; i++) {
|
|
slot = chip->slots[i];
|
|
if (!slot)
|
|
continue;
|
|
|
|
ret = sdhci_resume_host(slot->host);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sdhci_pci_runtime_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
|
|
struct sdhci_pci_chip *chip;
|
|
struct sdhci_pci_slot *slot;
|
|
int i, ret;
|
|
|
|
chip = pci_get_drvdata(pdev);
|
|
if (!chip)
|
|
return 0;
|
|
|
|
for (i = 0; i < chip->num_slots; i++) {
|
|
slot = chip->slots[i];
|
|
if (!slot)
|
|
continue;
|
|
|
|
ret = sdhci_runtime_suspend_host(slot->host);
|
|
|
|
if (ret)
|
|
goto err_pci_runtime_suspend;
|
|
}
|
|
|
|
if (chip->fixes && chip->fixes->suspend) {
|
|
ret = chip->fixes->suspend(chip);
|
|
if (ret)
|
|
goto err_pci_runtime_suspend;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_pci_runtime_suspend:
|
|
while (--i >= 0)
|
|
sdhci_runtime_resume_host(chip->slots[i]->host);
|
|
return ret;
|
|
}
|
|
|
|
static int sdhci_pci_runtime_resume(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
|
|
struct sdhci_pci_chip *chip;
|
|
struct sdhci_pci_slot *slot;
|
|
int i, ret;
|
|
|
|
chip = pci_get_drvdata(pdev);
|
|
if (!chip)
|
|
return 0;
|
|
|
|
if (chip->fixes && chip->fixes->resume) {
|
|
ret = chip->fixes->resume(chip);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
for (i = 0; i < chip->num_slots; i++) {
|
|
slot = chip->slots[i];
|
|
if (!slot)
|
|
continue;
|
|
|
|
ret = sdhci_runtime_resume_host(slot->host);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#else /* CONFIG_PM */
|
|
|
|
#define sdhci_pci_suspend NULL
|
|
#define sdhci_pci_resume NULL
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
static const struct dev_pm_ops sdhci_pci_pm_ops = {
|
|
.suspend = sdhci_pci_suspend,
|
|
.resume = sdhci_pci_resume,
|
|
SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
|
|
sdhci_pci_runtime_resume, NULL)
|
|
};
|
|
|
|
/*****************************************************************************\
|
|
* *
|
|
* Device probing/removal *
|
|
* *
|
|
\*****************************************************************************/
|
|
|
|
static struct sdhci_pci_slot *sdhci_pci_probe_slot(
|
|
struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
|
|
int slotno)
|
|
{
|
|
struct sdhci_pci_slot *slot;
|
|
struct sdhci_host *host;
|
|
int ret, bar = first_bar + slotno;
|
|
|
|
if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
|
|
dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
|
|
return ERR_PTR(-ENODEV);
|
|
}
|
|
|
|
if (pci_resource_len(pdev, bar) < 0x100) {
|
|
dev_err(&pdev->dev, "Invalid iomem size. You may "
|
|
"experience problems.\n");
|
|
}
|
|
|
|
if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
|
|
dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
|
|
return ERR_PTR(-ENODEV);
|
|
}
|
|
|
|
if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
|
|
dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
|
|
return ERR_PTR(-ENODEV);
|
|
}
|
|
|
|
host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
|
|
if (IS_ERR(host)) {
|
|
dev_err(&pdev->dev, "cannot allocate host\n");
|
|
return ERR_CAST(host);
|
|
}
|
|
|
|
slot = sdhci_priv(host);
|
|
|
|
slot->chip = chip;
|
|
slot->host = host;
|
|
slot->pci_bar = bar;
|
|
slot->rst_n_gpio = -EINVAL;
|
|
slot->cd_gpio = -EINVAL;
|
|
slot->cd_idx = -1;
|
|
|
|
/* Retrieve platform data if there is any */
|
|
if (*sdhci_pci_get_data)
|
|
slot->data = sdhci_pci_get_data(pdev, slotno);
|
|
|
|
if (slot->data) {
|
|
if (slot->data->setup) {
|
|
ret = slot->data->setup(slot->data);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "platform setup failed\n");
|
|
goto free;
|
|
}
|
|
}
|
|
slot->rst_n_gpio = slot->data->rst_n_gpio;
|
|
slot->cd_gpio = slot->data->cd_gpio;
|
|
}
|
|
|
|
host->hw_name = "PCI";
|
|
host->ops = &sdhci_pci_ops;
|
|
host->quirks = chip->quirks;
|
|
host->quirks2 = chip->quirks2;
|
|
|
|
host->irq = pdev->irq;
|
|
|
|
ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "cannot request region\n");
|
|
goto cleanup;
|
|
}
|
|
|
|
host->ioaddr = pci_ioremap_bar(pdev, bar);
|
|
if (!host->ioaddr) {
|
|
dev_err(&pdev->dev, "failed to remap registers\n");
|
|
ret = -ENOMEM;
|
|
goto release;
|
|
}
|
|
|
|
if (chip->fixes && chip->fixes->probe_slot) {
|
|
ret = chip->fixes->probe_slot(slot);
|
|
if (ret)
|
|
goto unmap;
|
|
}
|
|
|
|
if (gpio_is_valid(slot->rst_n_gpio)) {
|
|
if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
|
|
gpio_direction_output(slot->rst_n_gpio, 1);
|
|
slot->host->mmc->caps |= MMC_CAP_HW_RESET;
|
|
slot->hw_reset = sdhci_pci_gpio_hw_reset;
|
|
} else {
|
|
dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
|
|
slot->rst_n_gpio = -EINVAL;
|
|
}
|
|
}
|
|
|
|
host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
|
|
host->mmc->slotno = slotno;
|
|
host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
|
|
|
|
if (slot->cd_idx >= 0 &&
|
|
mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
|
|
slot->cd_override_level, 0, NULL)) {
|
|
dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
|
|
slot->cd_idx = -1;
|
|
}
|
|
|
|
ret = sdhci_add_host(host);
|
|
if (ret)
|
|
goto remove;
|
|
|
|
sdhci_pci_add_own_cd(slot);
|
|
|
|
/*
|
|
* Check if the chip needs a separate GPIO for card detect to wake up
|
|
* from runtime suspend. If it is not there, don't allow runtime PM.
|
|
* Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
|
|
*/
|
|
if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
|
|
!gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
|
|
chip->allow_runtime_pm = false;
|
|
|
|
return slot;
|
|
|
|
remove:
|
|
if (gpio_is_valid(slot->rst_n_gpio))
|
|
gpio_free(slot->rst_n_gpio);
|
|
|
|
if (chip->fixes && chip->fixes->remove_slot)
|
|
chip->fixes->remove_slot(slot, 0);
|
|
|
|
unmap:
|
|
iounmap(host->ioaddr);
|
|
|
|
release:
|
|
pci_release_region(pdev, bar);
|
|
|
|
cleanup:
|
|
if (slot->data && slot->data->cleanup)
|
|
slot->data->cleanup(slot->data);
|
|
|
|
free:
|
|
sdhci_free_host(host);
|
|
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
|
|
{
|
|
int dead;
|
|
u32 scratch;
|
|
|
|
sdhci_pci_remove_own_cd(slot);
|
|
|
|
dead = 0;
|
|
scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
|
|
if (scratch == (u32)-1)
|
|
dead = 1;
|
|
|
|
sdhci_remove_host(slot->host, dead);
|
|
|
|
if (gpio_is_valid(slot->rst_n_gpio))
|
|
gpio_free(slot->rst_n_gpio);
|
|
|
|
if (slot->chip->fixes && slot->chip->fixes->remove_slot)
|
|
slot->chip->fixes->remove_slot(slot, dead);
|
|
|
|
if (slot->data && slot->data->cleanup)
|
|
slot->data->cleanup(slot->data);
|
|
|
|
pci_release_region(slot->chip->pdev, slot->pci_bar);
|
|
|
|
sdhci_free_host(slot->host);
|
|
}
|
|
|
|
static void sdhci_pci_runtime_pm_allow(struct device *dev)
|
|
{
|
|
pm_runtime_put_noidle(dev);
|
|
pm_runtime_allow(dev);
|
|
pm_runtime_set_autosuspend_delay(dev, 50);
|
|
pm_runtime_use_autosuspend(dev);
|
|
pm_suspend_ignore_children(dev, 1);
|
|
}
|
|
|
|
static void sdhci_pci_runtime_pm_forbid(struct device *dev)
|
|
{
|
|
pm_runtime_forbid(dev);
|
|
pm_runtime_get_noresume(dev);
|
|
}
|
|
|
|
static int sdhci_pci_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
struct sdhci_pci_chip *chip;
|
|
struct sdhci_pci_slot *slot;
|
|
|
|
u8 slots, first_bar;
|
|
int ret, i;
|
|
|
|
BUG_ON(pdev == NULL);
|
|
BUG_ON(ent == NULL);
|
|
|
|
dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
|
|
(int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
|
|
|
|
ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
|
|
if (ret)
|
|
return ret;
|
|
|
|
slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
|
|
dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
|
|
if (slots == 0)
|
|
return -ENODEV;
|
|
|
|
BUG_ON(slots > MAX_SLOTS);
|
|
|
|
ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
|
|
if (ret)
|
|
return ret;
|
|
|
|
first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
|
|
|
|
if (first_bar > 5) {
|
|
dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = pci_enable_device(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
|
|
if (!chip) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
chip->pdev = pdev;
|
|
chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
|
|
if (chip->fixes) {
|
|
chip->quirks = chip->fixes->quirks;
|
|
chip->quirks2 = chip->fixes->quirks2;
|
|
chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
|
|
}
|
|
chip->num_slots = slots;
|
|
|
|
pci_set_drvdata(pdev, chip);
|
|
|
|
if (chip->fixes && chip->fixes->probe) {
|
|
ret = chip->fixes->probe(chip);
|
|
if (ret)
|
|
goto free;
|
|
}
|
|
|
|
slots = chip->num_slots; /* Quirk may have changed this */
|
|
|
|
for (i = 0; i < slots; i++) {
|
|
slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
|
|
if (IS_ERR(slot)) {
|
|
for (i--; i >= 0; i--)
|
|
sdhci_pci_remove_slot(chip->slots[i]);
|
|
ret = PTR_ERR(slot);
|
|
goto free;
|
|
}
|
|
|
|
chip->slots[i] = slot;
|
|
}
|
|
|
|
if (chip->allow_runtime_pm)
|
|
sdhci_pci_runtime_pm_allow(&pdev->dev);
|
|
|
|
return 0;
|
|
|
|
free:
|
|
pci_set_drvdata(pdev, NULL);
|
|
kfree(chip);
|
|
|
|
err:
|
|
pci_disable_device(pdev);
|
|
return ret;
|
|
}
|
|
|
|
static void sdhci_pci_remove(struct pci_dev *pdev)
|
|
{
|
|
int i;
|
|
struct sdhci_pci_chip *chip;
|
|
|
|
chip = pci_get_drvdata(pdev);
|
|
|
|
if (chip) {
|
|
if (chip->allow_runtime_pm)
|
|
sdhci_pci_runtime_pm_forbid(&pdev->dev);
|
|
|
|
for (i = 0; i < chip->num_slots; i++)
|
|
sdhci_pci_remove_slot(chip->slots[i]);
|
|
|
|
pci_set_drvdata(pdev, NULL);
|
|
kfree(chip);
|
|
}
|
|
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
static struct pci_driver sdhci_driver = {
|
|
.name = "sdhci-pci",
|
|
.id_table = pci_ids,
|
|
.probe = sdhci_pci_probe,
|
|
.remove = sdhci_pci_remove,
|
|
.driver = {
|
|
.pm = &sdhci_pci_pm_ops
|
|
},
|
|
};
|
|
|
|
module_pci_driver(sdhci_driver);
|
|
|
|
MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
|
|
MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
|
|
MODULE_LICENSE("GPL");
|