286 lines
7.7 KiB
C
286 lines
7.7 KiB
C
/*
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* Interrupt controller driver for PowerPC 4xx-based processors.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2004, 2005 Zultys Technologies
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*
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* Based on original code by
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* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
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* Armin Custer <akuster@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/stddef.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/ppc4xx_pic.h>
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#include <asm/machdep.h>
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/* See comment in include/arch-ppc/ppc4xx_pic.h
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* for more info about these two variables
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*/
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extern struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[NR_UICS]
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__attribute__ ((weak));
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extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
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#define IRQ_MASK_UIC0(irq) (1 << (31 - (irq)))
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#define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f)))
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#define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq)
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#define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq)
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#define IRQ_MASK_UIC3(irq) IRQ_MASK_UICx(irq)
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#define UIC_HANDLERS(n) \
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static void ppc4xx_uic##n##_enable(unsigned int irq) \
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{ \
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u32 mask = IRQ_MASK_UIC##n(irq); \
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if (irq_desc[irq].status & IRQ_LEVEL) \
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mtdcr(DCRN_UIC_SR(UIC##n), mask); \
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ppc_cached_irq_mask[n] |= mask; \
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mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
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} \
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\
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static void ppc4xx_uic##n##_disable(unsigned int irq) \
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{ \
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ppc_cached_irq_mask[n] &= ~IRQ_MASK_UIC##n(irq); \
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mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
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ACK_UIC##n##_PARENT \
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} \
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\
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static void ppc4xx_uic##n##_ack(unsigned int irq) \
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{ \
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u32 mask = IRQ_MASK_UIC##n(irq); \
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ppc_cached_irq_mask[n] &= ~mask; \
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mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
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mtdcr(DCRN_UIC_SR(UIC##n), mask); \
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ACK_UIC##n##_PARENT \
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} \
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\
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static void ppc4xx_uic##n##_end(unsigned int irq) \
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{ \
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unsigned int status = irq_desc[irq].status; \
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u32 mask = IRQ_MASK_UIC##n(irq); \
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if (status & IRQ_LEVEL) { \
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mtdcr(DCRN_UIC_SR(UIC##n), mask); \
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ACK_UIC##n##_PARENT \
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} \
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if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) { \
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ppc_cached_irq_mask[n] |= mask; \
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mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
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} \
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}
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#define DECLARE_UIC(n) \
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{ \
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.typename = "UIC"#n, \
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.enable = ppc4xx_uic##n##_enable, \
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.disable = ppc4xx_uic##n##_disable, \
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.ack = ppc4xx_uic##n##_ack, \
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.end = ppc4xx_uic##n##_end, \
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} \
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#if NR_UICS == 4
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#define ACK_UIC0_PARENT
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#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
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#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC);
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#define ACK_UIC3_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC3NC);
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UIC_HANDLERS(0);
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UIC_HANDLERS(1);
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UIC_HANDLERS(2);
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UIC_HANDLERS(3);
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static int ppc4xx_pic_get_irq(struct pt_regs *regs)
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{
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u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
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if (uic0 & UIC0_UIC1NC)
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return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
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else if (uic0 & UIC0_UIC2NC)
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return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
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else if (uic0 & UIC0_UIC3NC)
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return 128 - ffs(mfdcr(DCRN_UIC_MSR(UIC3)));
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else
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return uic0 ? 32 - ffs(uic0) : -1;
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}
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static void __init ppc4xx_pic_impl_init(void)
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{
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/* Enable cascade interrupts in UIC0 */
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ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC;
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mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC);
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mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
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}
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#elif NR_UICS == 3
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#define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
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#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
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#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
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UIC_HANDLERS(0);
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UIC_HANDLERS(1);
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UIC_HANDLERS(2);
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static int ppc4xx_pic_get_irq(struct pt_regs *regs)
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{
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u32 uicb = mfdcr(DCRN_UIC_MSR(UICB));
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if (uicb & UICB_UIC0NC)
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return 32 - ffs(mfdcr(DCRN_UIC_MSR(UIC0)));
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else if (uicb & UICB_UIC1NC)
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return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
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else if (uicb & UICB_UIC2NC)
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return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
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else
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return -1;
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}
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static void __init ppc4xx_pic_impl_init(void)
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{
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#if defined(CONFIG_440GX)
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/* Disable 440GP compatibility mode if it was enabled in firmware */
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SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~DCRN_SDR_MFR_PCM);
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#endif
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/* Configure Base UIC */
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mtdcr(DCRN_UIC_CR(UICB), 0);
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mtdcr(DCRN_UIC_TR(UICB), 0);
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mtdcr(DCRN_UIC_PR(UICB), 0xffffffff);
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mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
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mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
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}
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#elif NR_UICS == 2
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#define ACK_UIC0_PARENT
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#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
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UIC_HANDLERS(0);
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UIC_HANDLERS(1);
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static int ppc4xx_pic_get_irq(struct pt_regs *regs)
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{
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u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
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if (uic0 & UIC0_UIC1NC)
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return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
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else
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return uic0 ? 32 - ffs(uic0) : -1;
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}
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static void __init ppc4xx_pic_impl_init(void)
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{
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/* Enable cascade interrupt in UIC0 */
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ppc_cached_irq_mask[0] |= UIC0_UIC1NC;
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mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
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mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
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}
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#elif NR_UICS == 1
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#define ACK_UIC0_PARENT
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UIC_HANDLERS(0);
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static int ppc4xx_pic_get_irq(struct pt_regs *regs)
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{
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u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
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return uic0 ? 32 - ffs(uic0) : -1;
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}
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static inline void ppc4xx_pic_impl_init(void)
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{
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}
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#endif
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static struct ppc4xx_uic_impl {
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struct hw_interrupt_type decl;
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int base; /* Base DCR number */
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} __uic[] = {
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{ .decl = DECLARE_UIC(0), .base = UIC0 },
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#if NR_UICS > 1
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{ .decl = DECLARE_UIC(1), .base = UIC1 },
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#if NR_UICS > 2
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{ .decl = DECLARE_UIC(2), .base = UIC2 },
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#if NR_UICS > 3
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{ .decl = DECLARE_UIC(3), .base = UIC3 },
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#endif
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#endif
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#endif
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};
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static inline int is_level_sensitive(int irq)
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{
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u32 tr = mfdcr(DCRN_UIC_TR(__uic[irq >> 5].base));
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return (tr & IRQ_MASK_UICx(irq)) == 0;
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}
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void __init ppc4xx_pic_init(void)
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{
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int i;
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unsigned char *eirqs = ppc4xx_uic_ext_irq_cfg;
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for (i = 0; i < NR_UICS; ++i) {
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int base = __uic[i].base;
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/* Disable everything by default */
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ppc_cached_irq_mask[i] = 0;
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mtdcr(DCRN_UIC_ER(base), 0);
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/* We don't use critical interrupts */
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mtdcr(DCRN_UIC_CR(base), 0);
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/* Configure polarity and triggering */
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if (ppc4xx_core_uic_cfg) {
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struct ppc4xx_uic_settings *p = ppc4xx_core_uic_cfg + i;
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u32 mask = p->ext_irq_mask;
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u32 pr = mfdcr(DCRN_UIC_PR(base)) & mask;
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u32 tr = mfdcr(DCRN_UIC_TR(base)) & mask;
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/* "Fixed" interrupts (on-chip devices) */
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pr |= p->polarity & ~mask;
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tr |= p->triggering & ~mask;
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/* Merge external IRQs settings if board port
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* provided them
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*/
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if (eirqs && mask) {
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pr &= ~mask;
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tr &= ~mask;
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while (mask) {
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/* Extract current external IRQ mask */
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u32 eirq_mask = 1 << __ilog2(mask);
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if (!(*eirqs & IRQ_SENSE_LEVEL))
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tr |= eirq_mask;
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if (*eirqs & IRQ_POLARITY_POSITIVE)
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pr |= eirq_mask;
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mask &= ~eirq_mask;
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++eirqs;
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}
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}
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mtdcr(DCRN_UIC_PR(base), pr);
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mtdcr(DCRN_UIC_TR(base), tr);
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}
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/* ACK any pending interrupts to prevent false
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* triggering after first enable
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*/
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mtdcr(DCRN_UIC_SR(base), 0xffffffff);
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}
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/* Perform optional implementation specific setup
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* (e.g. enable cascade interrupts for multi-UIC configurations)
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*/
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ppc4xx_pic_impl_init();
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/* Attach low-level handlers */
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for (i = 0; i < (NR_UICS << 5); ++i) {
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irq_desc[i].handler = &__uic[i >> 5].decl;
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if (is_level_sensitive(i))
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irq_desc[i].status |= IRQ_LEVEL;
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}
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ppc_md.get_irq = ppc4xx_pic_get_irq;
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}
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