92 lines
2.0 KiB
C
92 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/m32r/kernel/sys_m32r.c
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*
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* This file contains various random system calls that
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* have a non-standard calling sequence on the Linux/M32R platform.
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*
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* Taken from i386 version.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/fs.h>
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#include <linux/smp.h>
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#include <linux/sem.h>
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#include <linux/msg.h>
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#include <linux/shm.h>
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#include <linux/stat.h>
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#include <linux/syscalls.h>
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#include <linux/mman.h>
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#include <linux/file.h>
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#include <linux/utsname.h>
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#include <linux/ipc.h>
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#include <linux/uaccess.h>
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#include <asm/cachectl.h>
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#include <asm/cacheflush.h>
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#include <asm/syscall.h>
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#include <asm/unistd.h>
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/*
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* sys_tas() - test-and-set
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*/
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asmlinkage int sys_tas(int __user *addr)
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{
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int oldval;
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if (!access_ok(VERIFY_WRITE, addr, sizeof (int)))
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return -EFAULT;
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/* atomic operation:
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* oldval = *addr; *addr = 1;
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*/
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r4", "%1")
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" .fillinsn\n"
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"1:\n"
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" lock %0, @%1 -> unlock %2, @%1\n"
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"2:\n"
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/* NOTE:
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* The m32r processor can accept interrupts only
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* at the 32-bit instruction boundary.
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* So, in the above code, the "unlock" instruction
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* can be executed continuously after the "lock"
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* instruction execution without any interruptions.
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*/
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".section .fixup,\"ax\"\n"
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" .balign 4\n"
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"3: ldi %0, #%3\n"
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" seth r14, #high(2b)\n"
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" or3 r14, r14, #low(2b)\n"
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" jmp r14\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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" .balign 4\n"
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" .long 1b,3b\n"
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".previous\n"
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: "=&r" (oldval)
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: "r" (addr), "r" (1), "i"(-EFAULT)
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: "r14", "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r4"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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return oldval;
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}
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asmlinkage int sys_cacheflush(void *addr, int bytes, int cache)
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{
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/* This should flush more selectively ... */
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_flush_cache_all();
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return 0;
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}
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asmlinkage int sys_cachectl(char *addr, int nbytes, int op)
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{
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/* Not implemented yet. */
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return -ENOSYS;
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}
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